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Stratix Device Handbook, Volume 1
101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com
S5V1-3.3
Copyright (c) 2005 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Contents
Chapter Revision Dates .......................................................................... vii About This Handbook .............................................................................. ix
How to Find Information ........................................................................................................................ ix How to Contact Altera ............................................................................................................................. ix Typographic Conventions ........................................................................................................................ x
Section I. Stratix Device Family Data Sheet
Revision History ............................................................................................................................ Part I-1
Chapter 1. Introduction
Introduction ............................................................................................................................................ 1-1 Features ................................................................................................................................................... 1-2
Chapter 2. Stratix Architecture
Functional Description .......................................................................................................................... 2-1 Logic Array Blocks ................................................................................................................................ 2-3 LAB Interconnects ............................................................................................................................ 2-4 LAB Control Signals ......................................................................................................................... 2-5 Logic Elements ....................................................................................................................................... 2-6 LUT Chain & Register Chain .......................................................................................................... 2-8 addnsub Signal ................................................................................................................................. 2-8 LE Operating Modes ........................................................................................................................ 2-8 Clear & Preset Logic Control ........................................................................................................ 2-13 MultiTrack Interconnect ..................................................................................................................... 2-14 TriMatrix Memory ............................................................................................................................... 2-21 Memory Modes ............................................................................................................................... 2-22 Clear Signals .................................................................................................................................... 2-24 Parity Bit Support ........................................................................................................................... 2-24 Shift Register Support .................................................................................................................... 2-25 Memory Block Size ......................................................................................................................... 2-26 Independent Clock Mode .............................................................................................................. 2-44 Input/Output Clock Mode ........................................................................................................... 2-46 Read/Write Clock Mode ............................................................................................................... 2-49 Single-Port Mode ............................................................................................................................ 2-51 Multiplier Block .............................................................................................................................. 2-57 Adder/Output Blocks ................................................................................................................... 2-61 Modes of Operation ....................................................................................................................... 2-64
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Contents
Stratix Device Handbook, Volume 1
DSP Block Interface ........................................................................................................................ 2-70 PLLs & Clock Networks ..................................................................................................................... 2-73 Global & Hierarchical Clocking ................................................................................................... 2-73 Enhanced & Fast PLLs ................................................................................................................... 2-81 Enhanced PLLs ............................................................................................................................... 2-87 Fast PLLs ........................................................................................................................................ 2-100 I/O Structure ...................................................................................................................................... 2-104 Double-Data Rate I/O Pins ......................................................................................................... 2-111 External RAM Interfacing ........................................................................................................... 2-115 Programmable Drive Strength ................................................................................................... 2-119 Open-Drain Output ...................................................................................................................... 2-120 Slew-Rate Control ........................................................................................................................ 2-120 Bus Hold ........................................................................................................................................ 2-121 Programmable Pull-Up Resistor ................................................................................................ 2-122 Advanced I/O Standard Support .............................................................................................. 2-122 Differential On-Chip Termination ............................................................................................. 2-127 MultiVolt I/O Interface ............................................................................................................... 2-129 High-Speed Differential I/O Support ............................................................................................ 2-130 Dedicated Circuitry ...................................................................................................................... 2-137 Byte Alignment ............................................................................................................................. 2-140 Power Sequencing & Hot Socketing ............................................................................................... 2-140
Chapter 3. Configuration & Testing
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support ............................................................................ 3-1 SignalTap II Embedded Logic Analyzer ............................................................................................ 3-5 Configuration ......................................................................................................................................... 3-5 Operating Modes .............................................................................................................................. 3-5 Configuring Stratix FPGAs with JRunner .................................................................................... 3-7 Configuration Schemes ................................................................................................................... 3-7 Partial Reconfiguration .................................................................................................................... 3-7 Remote Update Configuration Modes .......................................................................................... 3-8 Stratix Automated Single Event Upset (SEU) Detection ................................................................ 3-12 Custom-Built Circuitry .................................................................................................................. 3-13 Software Interface ........................................................................................................................... 3-13 Temperature Sensing Diode ............................................................................................................... 3-13
Chapter 4. DC & Switching Characteristics
Operating Conditions ........................................................................................................................... 4-1 Power Consumption ........................................................................................................................... 4-17 Timing Model ....................................................................................................................................... 4-19 Preliminary & Final Timing .......................................................................................................... 4-19 Performance .................................................................................................................................... 4-20 Internal Timing Parameters .......................................................................................................... 4-22 External Timing Parameters ......................................................................................................... 4-33 Stratix External I/O Timing .......................................................................................................... 4-36 I/O Timing Measurement Methodology .................................................................................... 4-60 External I/O Delay Parameters .................................................................................................... 4-66
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Contents
Contents
Maximum Input & Output Clock Rates ...................................................................................... 4-76 High-Speed I/O Specification ........................................................................................................... 4-87 PLL Specifications ................................................................................................................................ 4-94 DLL Jitter ............................................................................................................................................. 4-102
Chapter 5. Reference & Ordering Information
Software .................................................................................................................................................. 5-1 Device Pin-Outs ..................................................................................................................................... 5-1 Ordering Information ........................................................................................................................... 5-1
Index
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Contents
Stratix Device Handbook, Volume 1
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Chapter Revision Dates
The chapters in this book, Stratix Device Handbook, Volume 1, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1. Introduction Revised: Part number:
July 2005 S51001-3.2
Chapter 2. Stratix Architecture Revised: July 2005 Part number: S51002-3.2 Chapter 3. Configuration & Testing Revised: July 2005 Part number: S51003-1.3 Chapter 4. DC & Switching Characteristics Revised: July 2005 Part number: S51004-3.3 Chapter 5. Reference & Ordering Information Revised: September 2004 Part number: S51005-2.1
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Chapter Revision Dates
Stratix Device Handbook, Volume 1
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About This Handbook
This handbook provides comprehensive information about the Altera(R) Stratix family of devices.
How to Find Information
You can find more information in the following ways:
The Adobe Acrobat Find feature, which searches the text of a PDF document. Click the binoculars toolbar icon to open the Find dialog box. Acrobat bookmarks, which serve as an additional table of contents in PDF documents. Thumbnail icons, which provide miniature previews of each page, provide a link to the pages. Numerous links, shown in green text, which allow you to jump to related information.
How to Contact Altera
Information Type
Technical support
For the most up-to-date information about Altera products, go to the Altera world-wide web site at www.altera.com. For technical support on this product, go to www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below. USA & Canada
www.altera.com/mysupport/ (800) 800-EPLD (3753) (7:00 a.m. to 5:00 p.m. Pacific Time)
All Other Locations
www.altera.com/mysupport/ +1 408-544-8767 7:00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time www.altera.com literature@altera.com + 1 408-544-7000 7:00 a.m. to 5:00 p.m. (GMT -8:00) Pacific Time ftp.altera.com
Product literature Altera literature services Non-technical customer service FTP site
www.altera.com literature@altera.com (800) 767-3753
ftp.altera.com
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ix
Typographic Conventions
Stratix Device Handbook, Volume 1
Typographic Conventions
Visual Cue
Bold Type with Initial Capital Letters bold type
This document uses the typographic conventions shown below.
Meaning
Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file. Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Designs. Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: , .pof file.
Italic Type with Initial Capital Letters Italic type
Initial Capital Letters "Subheading Title"
Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: "Typographic Conventions." Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.
Courier type
1., 2., 3., and a., b., c., etc. v 1 r f
Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets are used in a list of items when the sequence of the items is not important. The checkmark indicates a procedure that consists of one step only. The hand points to information that requires special attention. The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic.
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Section I. Stratix Device Family Data Sheet
This section provides the data sheet specifications for Stratix(R) devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Stratix devices. This section contains the following chapters:

Chapter 1, Introduction Chapter 2, Stratix Architecture Chapter 3, Configuration & Testing Chapter 4, DC & Switching Characteristics Chapter 5, Reference & Ordering Information
Revision History
Chapter
1
The table below shows the revision history for Chapters 1 through 5.
Date/Version
July 2005, v3.2 September 2004, v3.1 April 2004, v3.0

Changes Made
Minor content changes. Updated Table 1-6 on page 1-5. Main section page numbers changed on first page. Changed PCI-X to PCI-X 1.0 in "Features" on page 1-2. Global change from SignalTap to SignalTap II. The DSP blocks in "Features" on page 1-2 provide dedicated implementation of multipliers that are now "faster than 300 MHz." Updated -5 speed grade device information in Table 1-6. Add -8 speed grade device information. Format changes throughout chapter.
January 2004, v2.2 October 2003, v2.1 July 2003, v2.0

Altera Corporation
Section I-1
Stratix Device Family Data Sheet
Stratix Device Handbook, Volume 1
Chapter
2
Date/Version
July 2005 v3.2

Changes Made
Added "Clear Signals" section. Updated "Power Sequencing & Hot Socketing" section. Format changes. Updated fast regional clock networks description on page 2-73. Deleted the word preliminary from the "specification for the maximum time to relock is 100 s" on page 2-90. Added information about differential SSTL and HSTL outputs in "External Clock Outputs" on page 2-92. Updated notes in Figure 2-55 on page 2-93. Added information about m counter to "Clock Multiplication & Division" on page 2-101. Updated Note 1 in Table 2-58 on page 2-101. Updated description of "Clock Multiplication & Division" on page 2-88. Updated Table 2-22 on page 2-102. Added references to AN 349 and AN 329 to "External RAM Interfacing" on page 2-115. Table 2-25 on page 2-116: updated the table, updated Notes 3 and 4. Notes 4, 5, and 6, are now Notes 5, 6, and 7, respectively. Updated Table 2-26 on page 2-117. Added information about PCI Compliance to page 2-120. Table 2-32 on page 2-126: updated the table and deleted Note 1. Updated reference to device pin-outs now being available on the web on page 2-130. Added Notes 4 and 5 to Table 2-36 on page 2-130. Updated Note 3 in Table 2-37 on page 2-131. Updated Note 5 in Table 2-41 on page 2-135. Added note 3 to rows 11 and 12 in Table 2-18. Deleted "Stratix and Stratix GX Device PLL Availability" table. Added I/O standards row in Table 2-28 that support max and min strength. Row clk [1,3,8,10] was removed from Table 2-30. Added checkmarks in Enhanced column for LVPECL, 3.3-V PCML, LVDS, and HyperTransport technology rows in Table 2-32. Removed the Left and Right I/O Banks row in Table 2-34. Changed RCLK values in Figures 2-50 and 2-51. External RAM Interfacing section replaced. Added 672-pin BGA package information in Table 2-37. Removed support for series and parallel on-chip termination. Termination Technology renamed differential on-chip termination. Updated the number of channels per PLL in Tables 2-38 through 242. Updated Figures 2-65 and 2-67. Updated DDR I information. Updated Table 2-22. Added Tables 2-25, 2-29, 2-30, and 2-72. Updated Figures 2-59, 2-65, and 2-67. Updated the Lock Detect section.
September 2004, v3.1

April 2004, v3.0

November 2003, v2.2

October 2003, v2.1

Section I-2
Altera Corporation
Stratix Device Family Data Sheet
Chapter
2
Date/Version
July 2003, v2.0

Changes Made
Added reference on page 2-73 to Figures 2-50 and 2-51 for RCLK connections. Updated ranges for EPLL post-scale and pre-scale dividers on page 2-85. Updated PLL Reconfiguration frequency from 25 to 22 MHz on page 2-87. New requirement to assert are set signal each PLL when it has to reacquire lock on either a new clock after loss of lock (page 2-96). Updated max input frequency for CLK[1,3,8,10] from 462 to 500, Table 2-24. Renamed impedance matching to series termination throughout. Updated naming convention for DQS pins on page 2-112 to match pin tables. Added DDR SDRAM Performance Specification on page 2-117. Added external reference resistor values for terminator technology (page 2-136). Added Terminator Technology Specification on pages 2-137 and 2138. Updated Tables 2-45 to 2-49 to reflect PLL cross-bank support for high speed differential channels at full speed. Wire bond package performance specification for "high" speed channels was increased to 624 Mbps from 462 Mbps throughout chapter. Updated "Operating Modes" section. Updated "Temperature Sensing Diode" section. Updated "IEEE Std. 1149.1 (JTAG) Boundary-Scan Support" section. Updated "Configuration" section. Updated limits for JTAG chain of devices. Added new section, "Stratix Automated Single Event Upset (SEU) Detection" on page 3-12. Updated description of "Custom-Built Circuitry" on page 3-13. No new changes in Stratix Device Handbook v2.0. Updated Tables 4-6 and 4-30. Updated Tables 4-103 through 4-108. Updated Tables 4-114 through 4-124. Updated Table 4-129. Added Table 4-130.
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July 2005, v1.3

January 2005, v1.2 September 2004, v1.1

April 2003, v1.0 4 July 2005 v3.3

Altera Corporation
Section I-3
Stratix Device Family Data Sheet
Stratix Device Handbook, Volume 1
Chapter
4
Date/Version
January 2005, 3.2 September 2004, v3.1

Changes Made
Updated rise and fall input values. Updated Note 3 in Table 4-8 on page 4-4. Updated Table 4-10 on page 4-6. Updated Table 4-20 on page 4-12 through Table 4-23 on page 4-13. Added rows VIL(AC) and VIH(AC) to each table. Updated Table 4-26 on page 4-14 through Table 4-29 on page 4-15. Updated Table 4-31 on page 4-16. Updated description of "External Timing Parameters" on page 4-33. Updated Table 4-36 on page 4-20. Added signals tOUTCO, TXZ, and TZX to Figure 4-4 on page 4-33. Added rows tM512CLKENSU and tM512CLKENH to Table 4-40 on page 4-24. Added rows tM4CLKENSU and tM4CLKENH to Table 4-41 on page 4-24. Updated Note 2 in Table 4-54 on page 4-35. Added rows tMRAMCLKENSU and tMRAMCLKENH to Table 4-42 on page 4-25. Updated Table 4-46 on page 4-29. Updated Table 4-47 on page 4-29.
Section I-4
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Stratix Device Family Data Sheet
Chapter
4
Date/Version

Changes Made
Table 4-48 on page 4-30: added rows tM512CLKSENSU and tM512CLKENH, and updated symbol names. Updated power-up current (ICCINT) required to power a Stratix device on page 4-17. Updated Table 4-37 on page 4-22 through Table 4-43 on page 4-27. Table 4-49 on page 4-31: added rows tM4KCLKENSU, tM4KCLKENH, tM4KBESU, and tM4KBEH, deleted rows tM4KRADDRASU and tM4KRADDRH, and updated symbol names. Table 4-50 on page 4-31: added rows tMRAMCLKENSU, tMRAMCLKENH, tMRAMBESU, and tMRAMBEH, deleted rows tMRAMADDRASU and tMRAMRADDRH, and updated symbol names. Table 4-52 on page 4-34: updated table, deleted "Conditions" column, and added rows tXZ and tZX. Table 4-52 on page 4-34: updated table, deleted "Conditions" column, and added rows tXZ and tZX. Table 4-53 on page 4-34: updated table and added rows tXZPLL and tZXPLL. Updated Note 2 in Table 4-53 on page 4-34. Table 4-54 on page 4-35: updated table, deleted "Conditions" column, and added rows tXZPLL and tZXPLL. Updated Note 2 in Table 4-54 on page 4-35. Deleted Note 2 from Table 4-55 on page 4-36 through Table 4-66 on page 4-41. Updated Table 4-55 on page 4-36 through Table 4-96 on page 4-56. Added rows TXZ, TZX, TXZPLL, and TZXPLL. Added Note 4 to Table 4-101 on page 4-62. Deleted Note 1 from Table 4-67 on page 4-42 through Table 4-84 on page 4-50. Added new section "I/O Timing Measurement Methodology" on page 4-60. Deleted Note 1 from Table 4-67 on page 4-42 through Table 4-84 on page 4-50. Deleted Note 2 from Table 4-85 on page 4-51 through Table 4-96 on page 4-56. Added Note 4 to Table 4-101 on page 4-62. Table 4-102 on page 4-64: updated table and added Note 4. Updated description of "External I/O Delay Parameters" on page 4-66. Added Note 1 to Table 4-109 on page 4-73 and Table 4-110 on page 4-74. Updated Table 4-103 on page 4-66 through Table 4-110 on page 4-74. Deleted Note 2 from Table 4-103 on page 4-66 through Table 4-106 on page 4-69. Added new paragraph about output adder delays on page 4-68. Updated Table 4-110 on page 4-74. Added Note 1 to Table 4-111 through Table 4-113 on page 4-75.

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Section I-5
Stratix Device Family Data Sheet
Stratix Device Handbook, Volume 1
Chapter
4
Date/Version

Changes Made
Updated Table 4-123 on page 4-85 through Table 4-126 on page 4-92. Updated Note 3 in Table 4-123 on page 4-85. Table 4-125 on page 4-88: moved to correct order in chapter, and updated table. Updated Table 4-126 on page 4-92. Updated Table 4-127 on page 4-94. Updated Table 4-128 on page 4-95. Table 4-129 on page 4-96: updated table and added Note 10. Updated Table 4-131 and Table 4-132 on page 4-100. Updated Table 4-110 on page 4-74. Updated Table 4-123 on page 4-85. Updated Table 4-124 on page 4-87. through Table 4-126 on page 4-92. Added Note 10 to Table 4-129 on page 4-96. Moved Table 4-127 on page 4-94 to correct order in the chapter. Updated Table 4-131 on page 4-100 through Table 4-132 on page 4-100. Deleted tXZ and tZX from Figure 4-4. Waveform was added to Figure 4-6. The minimum and maximum duty cycle values in Note 3 of Table 4-8 were moved to a new Table 4-9. Changes were made to values in SSTL-3 Class I and II rows in Table 4-17. Note 1 was added to Table 4-34. Added tSU_R and tSU_C rows in Table 4-38. Changed Table 4-55 title from "EP1S10 Column Pin Fast Regional Clock External I/O Timing Parameters" to "EP1S10 External I/O Timing on Column Pins Using Fast Regional Clock Networks." Changed values in Tables 4-46, 4-48 to 4-51, 4-128, and 4-131. Added tARESET row in Tables 4-127 to 4-132. Deleted -5 Speed Grade column in Tables 4-117 to 4-119 and 4-122 to 4-123. Fixed differential waveform in Figure 4-1. Added "Definition of I/O Skew" section. Added tSU and tCO_C rows and made changes to values in tPRE and tCLKHL rows in Table 4-46. Values changed in the tSU and tH rows in Table 4-47. Values changed in the tM4KCLKHL row in Table 4-49. Values changed in the tMRAMCLKHL row in Table 4-50. Added Table 4-51 to "Internal Timing Parameters" section. The timing information is preliminary in Tables 4-55 through 4-96. Table 4-111 was separated into 3 tables: Tables 4-111 to 4-113. Updated Tables 4-127 through 4-129.
April 2004, v3.0

November 2003, v2.2
Section I-6
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Stratix Device Family Data Sheet
Chapter
4
Date/Version
October 2003, v2.1

Changes Made
Added -8 speed grade information. Updated performance information in Table 4-36. Updated timing information in Tables 4-55 through 4-96. Updated delay information in Tables 4-103 through 4-108. Updated programmable delay information in Tables 4-100 and 4-103. Updated clock rates in Tables 4-114 through 4-123. Updated speed grade information in the introduction on page 4-1. Corrected figures 4-1 & 4-2 and Table 4-9 to reflect how VID and VOD are specified. Added note 6 to Table 4-32. Updated Stratix Performance Table 4-35. Updated EP1S60 and EP1S80 timing parameters in Tables 4-82 to 493. The Stratix timing models are final for all devices. Updated Stratix IOE programmable delay chains in Tables 4-100 to 4101. Added single-ended I/O standard output pin delay adders for loading in Table 4-102. Added spec for FPLL[10..7]CLK pins in Tables 4-104 and 4-107. Updated high-speed I/O specification for J=2 in Tables 4-114 and 4115. Updated EPLL specification and fast PLL specification in Tables 4116 to 4-120. Updated reference to device pin-outs on page 5-1 to indicate that device pin-outs are no longer included in this manual and are now available on the Altera web site. No new changes in Stratix Device Handbook v2.0.
July 2003, v2.0

5
September 2004, v2.1
April 2003, v1.0
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Section I-7
Stratix Device Family Data Sheet
Stratix Device Handbook, Volume 1
Section I-8
Altera Corporation
1. Introduction
S51001-3.2
Introduction
The Stratix(R) family of FPGAs is based on a 1.5-V, 0.13-m, all-layer copper SRAM process, with densities of up to 79,040 logic elements (LEs) and up to 7.5 Mbits of RAM. Stratix devices offer up to 22 digital signal processing (DSP) blocks with up to 176 (9-bit x 9-bit) embedded multipliers, optimized for DSP applications that enable efficient implementation of high-performance filters and multipliers. Stratix devices support various I/O standards and also offer a complete clock management solution with its hierarchical clock structure with up to 420-MHz performance and up to 12 phase-locked loops (PLLs). The following shows the main sections in the Stratix Device Family Data Sheet: Section Page
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 TriMatrix Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 Digital Signal Processing Block . . . . . . . . . . . . . . . . . . . . . . . . 2-52 PLLs & Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73 I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-104 High-Speed Differential I/O Support. . . . . . . . . . . . . . . . . . 2-130 Power Sequencing & Hot Socketing . . . . . . . . . . . . . . . . . . . 2-140 IEEE Std. 1149.1 (JTAG) Boundary-Scan Support. . . . . . . . . . 3-1 SignalTap II Embedded Logic Analyzer . . . . . . . . . . . . . . . . . 3-5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Temperature Sensing Diode. . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
Altera Corporation July 2005
1-1
Features
Features
The Stratix family offers the following features:

10,570 to 79,040 LEs; see Table 1-1 Up to 7,427,520 RAM bits (928,440 bytes) available without reducing logic resources TriMatrixTM memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers High-speed DSP blocks provide dedicated implementation of multipliers (faster than 300 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters Up to 16 global clocks with 22 clocking resources per device region Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting Support for numerous single-ended and differential I/O standards High-speed differential I/O support on up to 116 channels with up to 80 channels optimized for 840 megabits per second (Mbps) Support for high-speed networking and communications bus standards including RapidIO, UTOPIA IV, CSIX, HyperTransportTM technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4), and SFI-4 Differential on-chip termination support for LVDS Support for high-speed external memory, including zero bus turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM, double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM), and single data rate (SDR) SDRAM Support for 66-MHz PCI (64 and 32 bit) in -6 and faster speed-grade devices, support for 33-MHz PCI (64 and 32 bit) in -8 and faster speed-grade devices Support for 133-MHz PCI-X 1.0 in -5 speed-grade devices Support for 100-MHz PCI-X 1.0 in -6 and faster speed-grade devices Support for 66-MHz PCI-X 1.0 in -7 speed-grade devices Support for multiple intellectual property megafunctions from Altera MegaCore(R) functions and Altera Megafunction Partners Program (AMPPSM) megafunctions Support for remote configuration updates
1-2 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
Introduction
Table 1-1. Stratix Device Features -- EP1S10, EP1S20, EP1S25, EP1S30 Feature
LEs M512 RAM blocks (32 x 18 bits) M4K RAM blocks (128 x 36 bits) M-RAM blocks (4K x 144 bits) Total RAM bits DSP blocks Embedded multipliers (1) PLLs Maximum user I/O pins
EP1S10
10,570 94 60 1 920,448 6 48 6 426
EP1S20
18,460 194 82 2 1,669,248 10 80 6 586
EP1S25
25,660 224 138 2 1,944,576 10 80 6 706
EP1S30
32,470 295 171 4 3,317,184 12 96 10 726
Table 1-2. Stratix Device Features -- EP1S40, EP1S60, EP1S80 Feature
LEs M512 RAM blocks (32 x 18 bits) M4K RAM blocks (128 x 36 bits) M-RAM blocks (4K x 144 bits) Total RAM bits DSP blocks Embedded multipliers (1) PLLs Maximum user I/O pins Note to Tables 1-1 and 1-2:
(1)
EP1S40
41,250 384 183 4 3,423,744 14 112 12 822
EP1S60
57,120 574 292 6 5,215,104 18 144 12 1,022
EP1S80
79,040 767 364 9 7,427,520 22 176 12 1,238
This parameter lists the total number of 9 x 9-bit multipliers for each device. For the total number of 18 x 18-bit multipliers per device, divide the total number of 9 x 9-bit multipliers by 2. For the total number of 36 x 36-bit multipliers per device, divide the total number of 9 x 9-bit multipliers by 8.
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Features
Stratix devices are available in space-saving FineLine BGA(R) and ball-grid array (BGA) packages (see Tables 1-3 through 1-5). All Stratix devices support vertical migration within the same package (for example, you can migrate between the EP1S10, EP1S20, and EP1S25 devices in the 672pin BGA package). Vertical migration means that you can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For I/O pin migration across densities, you must cross-reference the available I/O pins using the device pin-outs for all planned densities of a given package type to identify which I/O pins are migrational. The Quartus(R) II software can automatically cross reference and place all pins except differential pins for migration when given a device migration list. You must use the pinouts for each device to verify the differential placement migration. A future version of the Quartus II software will support differential pin migration.
Table 1-3. Stratix Package Options & I/O Pin Counts Device
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 Note to Table 1-3:
(1) All I/O pin counts include 20 dedicated clock input pins (clk[15..0]p, clk0n, clk2n, clk9n, and clk11n) that can be used for data inputs.
672-Pin BGA
345 426 473
956-Pin BGA
484-Pin FineLine BGA
335 361
672-Pin FineLine BGA
345 426 473
780-Pin FineLine BGA
426 586 597 597 615
1,020-Pin FineLine BGA
1,508-Pin FineLine BGA
706 726 773 773 773 822 1,022 1,203
683 683 683 683
Table 1-4. Stratix BGA Package Sizes Dimension
Pitch (mm) Area (mm2) Length x width (mm x mm)
672 Pin
1.27 1,225 35 x 35
956 Pin
1.27 1,600 40 x 40
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Introduction
Table 1-5. Stratix FineLine BGA Package Sizes Dimension
Pitch (mm) Area (mm2) Length x width (mm x mm)
484 Pin
1.00 529 23 x 23
672 Pin
1.00 729 27 x 27
780 Pin
1.00 841 29 x 29
1,020 Pin
1.00 1,089 33 x 33
1,508 Pin
1.00 1,600 40 x 40
Stratix devices are available in up to four speed grades, -5, -6, -7, and -8, with -5 being the fastest. Table 1-6 shows Stratix device speed-grade offerings.
Table 1-6. Stratix Device Speed Grades Device
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
672-Pin BGA
-6, -7 -6, -7 -6, -7
956-Pin BGA
484-Pin FineLine BGA
-5, -6, -7 -5, -6, -7
672-Pin FineLine BGA
-6, -7 -6, -7 -6, -7, -8
780-Pin FineLine BGA
-5, -6, -7 -5, -6, -7 -5, -6, -7 -5, -6, -7, -8 -5, -6, -7, -8
1,020-Pin FineLine BGA
1,508-Pin FineLine BGA
-5, -6, -7 -5, -6, -7 -5, -6, -7 -5, -6, -7 -5, -6, -7 -5, -6, -7 -6, -7 -5, -6, -7
-5, -6, -7 -5, -6, -7 -6, -7 -6, -7
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Features
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2. Stratix Architecture
S51002-3.2
Functional Description
Stratix(R) devices contain a two-dimensional row- and column-based architecture to implement custom logic. A series of column and row interconnects of varying length and speed provide signal interconnects between logic array blocks (LABs), memory block structures, and DSP blocks. The logic array consists of LABs, with 10 logic elements (LEs) in each LAB. An LE is a small unit of logic providing efficient implementation of user logic functions. LABs are grouped into rows and columns across the device. M512 RAM blocks are simple dual-port memory blocks with 512 bits plus parity (576 bits). These blocks provide dedicated simple dual-port or single-port memory up to 18-bits wide at up to 318 MHz. M512 blocks are grouped into columns across the device in between certain LABs. M4K RAM blocks are true dual-port memory blocks with 4K bits plus parity (4,608 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 36-bits wide at up to 291 MHz. These blocks are grouped into columns across the device in between certain LABs. M-RAM blocks are true dual-port memory blocks with 512K bits plus parity (589,824 bits). These blocks provide dedicated true dual-port, simple dual-port, or single-port memory up to 144-bits wide at up to 269 MHz. Several M-RAM blocks are located individually or in pairs within the device's logic array. Digital signal processing (DSP) blocks can implement up to either eight full-precision 9 x 9-bit multipliers, four full-precision 18 x 18-bit multipliers, or one full-precision 36 x 36-bit multiplier with add or subtract features. These blocks also contain 18-bit input shift registers for digital signal processing applications, including FIR and infinite impulse response (IIR) filters. DSP blocks are grouped into two columns in each device. Each Stratix device I/O pin is fed by an I/O element (IOE) located at the end of LAB rows and columns around the periphery of the device. I/O pins support numerous single-ended and differential I/O standards. Each IOE contains a bidirectional I/O buffer and six registers for registering input, output, and output-enable signals. When used with
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2-1
Functional Description
dedicated clocks, these registers provide exceptional performance and interface support with external memory devices such as DDR SDRAM, FCRAM, ZBT, and QDR SRAM devices. High-speed serial interface channels support transfers at up to 840 Mbps using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology I/O standards. Figure 2-1 shows an overview of the Stratix device. Figure 2-1. Stratix Block Diagram
M512 RAM Blocks for Dual-Port Memory, Shift Registers, & FIFO Buffers DSP Blocks for Multiplication and Full Implementation of FIR Filters M4K RAM Blocks for True Dual-Port Memory & Other Embedded Memory Functions IOEs Support DDR, PCI, GTL+, SSTL-3, SSTL-2, HSTL, LVDS, LVPECL, PCML, HyperTransport & other I/O Standards
IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs IOEs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs
IOEs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs
IOEs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs LABs
IOEs LABs LABs LABs LABs
M-RAM Block
LABs
DSP Block
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Stratix Architecture
The number of M512 RAM, M4K RAM, and DSP blocks varies by device along with row and column numbers and M-RAM blocks. Table 2-1 lists the resources available in Stratix devices.
Table 2-1. Stratix Device Resources Device
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
M512 RAM M4K RAM Columns/Blocks Columns/Blocks
4 / 94 6 / 194 6 / 224 7 / 295 8 / 384 10 / 574 11 / 767 2 / 60 2 / 82 3 / 138 3 / 171 3 / 183 4 / 292 4 / 364
M-RAM Blocks
1 2 2 4 4 6 9
DSP Block Columns/Blocks
2/6 2 / 10 2 / 10 2 / 12 2 / 14 2 / 18 2 / 22
LAB Columns
40 52 62 67 77 90 101
LAB Rows
30 41 46 57 61 73 91
Logic Array Blocks
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, local interconnect, LUT chain, and register chain connection lines. The local interconnect transfers signals between LEs in the same LAB. LUT chain connections transfer the output of one LE's LUT to the adjacent LE for fast sequential LUT connections within the same LAB. Register chain connections transfer the output of one LE's register to the adjacent LE's register within an LAB. The Quartus(R) II Compiler places associated logic within an LAB or adjacent LABs, allowing the use of local, LUT chain, and register chain connections for performance and area efficiency. Figure 2-2 shows the Stratix LAB.
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Logic Array Blocks
Figure 2-2. Stratix LAB Structure
Row Interconnects of Variable Speed & Length
Direct link interconnect from adjacent block
Direct link interconnect from adjacent block
Direct link interconnect to adjacent block
Direct link interconnect to adjacent block
Local Interconnect
LAB
Three-Sided Architecture--Local Interconnect is Driven from Either Side by Columns & LABs, & from Above by Rows
Column Interconnects of Variable Speed & Length
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB local interconnect is driven by column and row interconnects and LE outputs within the same LAB. Neighboring LABs, M512 RAM blocks, M4K RAM blocks, or DSP blocks from the left and right can also drive an LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each LE can drive 30 other LEs through fast local and direct link interconnects. Figure 2-3 shows the direct link connection.
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Stratix Architecture
Figure 2-3. Direct Link Connection
Direct link interconnect from left LAB, TriMatrix memory block, DSP block, or IOE output Direct link interconnect from right LAB, TriMatrix memory block, DSP block, or IOE output
Direct link interconnect to left Local Interconnect LAB
Direct link interconnect to right
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its LEs. The control signals include two clocks, two clock enables, two asynchronous clears, synchronous clear, asynchronous preset/load, synchronous load, and add/subtract control signals. This gives a maximum of 10 control signals at a time. Although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions. Each LAB can use two clocks and two clock enable signals. Each LAB's clock and clock enable signals are linked. For example, any LE in a particular LAB using the labclk1 signal will also use labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses both LAB-wide clock signals. De-asserting the clock enable signal will turn off the LAB-wide clock. Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. The asynchronous load acts as a preset when the asynchronous load data input is tied high.
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Logic Elements
With the LAB-wide addnsub control signal, a single LE can implement a one-bit adder and subtractor. This saves LE resources and improves performance for logic functions such as DSP correlators and signed multipliers that alternate between addition and subtraction depending on data. The LAB row clocks [7..0] and LAB local interconnect generate the LABwide control signals. The MultiTrackTM interconnect's inherent low skew allows clock and control signal distribution in addition to data. Figure 2-4 shows the LAB control signal generation circuit. Figure 2-4. LAB-Wide Control Signals
Dedicated Row LAB Clocks Local Interconnect Local Interconnect 8
Local Interconnect Local Interconnect Local Interconnect Local Interconnect labclk1
labclkena1
labclkena2
syncload
labclr2
addnsub
labclk2
asyncload or labpre
labclr1
synclr
Logic Elements
The smallest unit of logic in the Stratix architecture, the LE, is compact and provides advanced features with efficient logic utilization. Each LE contains a four-input LUT, which is a function generator that can implement any function of four variables. In addition, each LE contains a programmable register and carry chain with carry select capability. A single LE also supports dynamic single bit addition or subtraction mode selectable by an LAB-wide control signal. Each LE drives all types of interconnects: local, row, column, LUT chain, register chain, and direct link interconnects. See Figure 2-5.
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Stratix Architecture
Figure 2-5. Stratix LE
Register chain routing from previous LE LAB-wide Register Bypass Synchronous Load LAB-wide Packed Synchronous Register Select Clear
LAB Carry-In addnsub Carry-In1 Carry-In0
Programmable Register LUT chain routing to next LE Row, column, and direct link routing
data1 data2 data3 data4
ENA CLRN
Look-Up Table (LUT)
Carry Chain
Synchronous Load and Clear Logic
PRN/ALD D Q ADATA
Row, column, and direct link routing
labclr1 labclr2 labpre/aload Chip-Wide Reset
Asynchronous Clear/Preset/ Load Logic
Local Routing
Clock & Clock Enable Select labclk1 labclk2 labclkena1 labclkena2
Register Feedback
Register chain output
Carry-Out0 Carry-Out1 LAB Carry-Out
Each LE's programmable register can be configured for D, T, JK, or SR operation. Each register has data, true asynchronous load data, clock, clock enable, clear, and asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any internal logic can drive the register's clock and clear control signals. Either general-purpose I/O pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous data. The asynchronous load data input comes from the data3 input of the LE. For combinatorial functions, the register is bypassed and the output of the LUT drives directly to the outputs of the LE. Each LE has three outputs that drive the local, row, and column routing resources. The LUT or register output can drive these three outputs independently. Two LE outputs drive column or row and direct link routing connections and one drives local interconnect resources. This allows the LUT to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and the LUT for unrelated
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Logic Elements
functions. Another special packing mode allows the register output to feed back into the LUT of the same LE so that the register is packed with its own fan-out LUT. This provides another mechanism for improved fitting. The LE can also drive out registered and unregistered versions of the LUT output.
LUT Chain & Register Chain
In addition to the three general routing outputs, the LEs within an LAB have LUT chain and register chain outputs. LUT chain connections allow LUTs within the same LAB to cascade together for wide input functions. Register chain outputs allow registers within the same LAB to cascade together. The register chain output allows an LAB to use LUTs for a single combinatorial function and the registers to be used for an unrelated shift register implementation. These resources speed up connections between LABs while saving local interconnect resources. See "MultiTrack Interconnect" on page 2-14 for more information on LUT chain and register chain connections.
addnsub Signal
The LE's dynamic adder/subtractor feature saves logic resources by using one set of LEs to implement both an adder and a subtractor. This feature is controlled by the LAB-wide control signal addnsub. The addnsub signal sets the LAB to perform either A + B or A - B. The LUT computes addition, and subtraction is computed by adding the two's complement of the intended subtractor. The LAB-wide signal converts to two's complement by inverting the B bits within the LAB and setting carry-in = 1 to add one to the least significant bit (LSB). The LSB of an adder/subtractor must be placed in the first LE of the LAB, where the LAB-wide addnsub signal automatically sets the carry-in to 1. The Quartus II Compiler automatically places and uses the adder/subtractor feature when using adder/subtractor parameterized functions.
LE Operating Modes
The Stratix LE can operate in one of the following modes:

Normal mode Dynamic arithmetic mode
Each mode uses LE resources differently. In each mode, eight available inputs to the LE--the four data inputs from the LAB local interconnect; carry-in0 and carry-in1 from the previous LE; the LAB carry-in from the previous carry-chain LAB; and the register chain connection-- are directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear,
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Stratix Architecture
asynchronous preset load, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all LE modes. The addnsub control signal is allowed in arithmetic mode. The Quartus II software, in conjunction with parameterized functions such as library of parameterized modules (LPM) functions, automatically chooses the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. If required, you can also create special-purpose functions that specify which LE operating mode to use for optimal performance.
Normal Mode
The normal mode is suitable for general logic applications and combinatorial functions. In normal mode, four data inputs from the LAB local interconnect are inputs to a four-input LUT (see Figure 2-6). The Quartus II Compiler automatically selects the carry-in or the data3 signal as one of the inputs to the LUT. Each LE can use LUT chain connections to drive its combinatorial output directly to the next LE in the LAB. Asynchronous load data for the register comes from the data3 input of the LE. LEs in normal mode support packed registers. Figure 2-6. LE in Normal Mode
sload sclear (LAB Wide) (LAB Wide) Register chain connection aload (LAB Wide)
addnsub (LAB Wide)
(1)
data1 data2 data3 cin (from cout of previous LE) data4
4-Input LUT
ALD/PRE ADATA Q D ENA CLRN
Row, column, and direct link routing Row, column, and direct link routing
clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide)
Local routing
LUT chain connection Register chain output
Register Feedback
Note to Figure 2-6:
(1) This signal is only allowed in normal mode if the LE is at the end of an adder/subtractor chain.
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Logic Elements
Dynamic Arithmetic Mode
The dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. An LE in dynamic arithmetic mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first two 2-input LUTs compute two summations based on a possible carry-in of 1 or 0; the other two LUTs generate carry outputs for the two chains of the carry select circuitry. As shown in Figure 2-7, the LAB carry-in signal selects either the carry-in0 or carry-in1 chain. The selected chain's logic level in turn determines which parallel sum is generated as a combinatorial or registered output. For example, when implementing an adder, the sum output is the selection of two possible calculated sums: data1 + data2 + carry-in0 or data1 + data2 + carry-in1. The other two LUTs use the data1 and data2 signals to generate two possible carry-out signals--one for a carry of 1 and the other for a carry of 0. The carry-in0 signal acts as the carry select for the carry-out0 output and carry-in1 acts as the carry select for the carry-out1 output. LEs in arithmetic mode can drive out registered and unregistered versions of the LUT output. The dynamic arithmetic mode also offers clock enable, counter enable, synchronous up/down control, synchronous clear, synchronous load, and dynamic adder/subtractor options. The LAB local interconnect data inputs generate the counter enable and synchronous up/down control signals. The synchronous clear and synchronous load options are LABwide signals that affect all registers in the LAB. The Quartus II software automatically places any registers that are not used by the counter into other LABs. The addnsub LAB-wide signal controls whether the LE acts as an adder or subtractor.
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Stratix Architecture
Figure 2-7. LE in Dynamic Arithmetic Mode
LAB Carry-In Carry-In0 Carry-In1 addnsub (LAB Wide) (1) sload sclear (LAB Wide) (LAB Wide) Register chain connection aload (LAB Wide)
data1 data2 data3
LUT
ALD/PRE ADATA Q D ENA CLRN
Row, column, and direct link routing Row, column, and direct link routing
LUT
LUT
clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide)
Local routing
LUT
LUT chain connection Register chain output Register Feedback
Carry-Out0
Carry-Out1
Note to Figure 2-7:
(1) The addnsub signal is tied to the carry input for the first LE of a carry chain only.
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between LEs in arithmetic mode. The carry-select chain uses the redundant carry calculation to increase the speed of carry functions. The LE is configured to calculate outputs for a possible carry-in of 1 and carry-in of 0 in parallel. The carry-in0 and carry-in1 signals from a lower-order bit feed forward into the higher-order bit via the parallel carry chain and feed into both the LUT and the next portion of the carry chain. Carry-select chains can begin in any LE within an LAB. The speed advantage of the carry-select chain is in the parallel precomputation of carry chains. Since the LAB carry-in selects the precomputed carry chain, not every LE is in the critical path. Only the propagation delay between LAB carry-in generation (LE 5 and LE 10) are now part of the critical path. This feature allows the Stratix architecture to implement high-speed counters, adders, multipliers, parity functions, and comparators of arbitrary width.
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Logic Elements
Figure 2-8 shows the carry-select circuitry in an LAB for a 10-bit full adder. One portion of the LUT generates the sum of two bits using the input signals and the appropriate carry-in bit; the sum is routed to the output of the LE. The register can be bypassed for simple adders or used for accumulator functions. Another portion of the LUT generates carryout bits. An LAB-wide carry in bit selects which chain is used for the addition of given inputs. The carry-in signal for each chain, carry-in0 or carry-in1, selects the carry-out to carry forward to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to an LE, where it is fed to local, row, or column interconnects. The Quartus II Compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. Parameterized functions such as LPM functions automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 10 LEs by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically allowing fast horizontal connections to TriMatrixTM memory and DSP blocks. A carry chain can continue as far as a full column.
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Stratix Architecture
Figure 2-8. Carry Select Chain
LAB Carry-In A1 B1 A2 B2
0 LE1
1 Sum1
LAB Carry-In Carry-In0 Carry-In1
LE2
Sum2
LUT data1 data2 Sum LUT
A3 B3 A4 B4
LE3
Sum3
LE4
Sum4
LUT
A5 B5
LE5
Sum5
LUT
0 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 LE6
1 Sum6
Carry-Out0
Carry-Out1
LE7
Sum7
LE8
Sum8
LE9
Sum9
LE10
Sum10
LAB Carry-Out
Clear & Preset Logic Control
LAB-wide signals control the logic for the register's clear and preset signals. The LE directly supports an asynchronous clear and preset function. The register preset is achieved through the asynchronous load of a logic high. The direct asynchronous preset does not require a NOTgate push-back technique. Stratix devices support simultaneous preset/
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MultiTrack Interconnect
asynchronous load, and clear signals. An asynchronous clear signal takes precedence if both signals are asserted simultaneously. Each LAB supports up to two clears and one preset signal. In addition to the clear and preset ports, Stratix devices provide a chipwide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin. This chip-wide reset overrides all other control signals.
MultiTrack Interconnect
In the Stratix architecture, connections between LEs, TriMatrix memory, DSP blocks, and device I/O pins are provided by the MultiTrack interconnect structure with DirectDriveTM technology. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for inter- and intra-design block connectivity. The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance. DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement within the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycles that typically follow design changes and additions. The MultiTrack interconnect consists of row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. Dedicated row interconnects route signals to and from LABs, DSP blocks, and TriMatrix memory within the same row. These row resources include:

Direct link interconnects between LABs and adjacent blocks. R4 interconnects traversing four blocks to the right or left. R8 interconnects traversing eight blocks to the right or left. R24 row interconnects for high-speed access across the length of the device.
The direct link interconnect allows an LAB, DSP block, or TriMatrix memory block to drive into the local interconnect of its left and right neighbors and then back into itself. Only one side of a M-RAM block interfaces with direct link and row interconnects. This provides fast communication between adjacent LABs and/or blocks without using row interconnect resources. The R4 interconnects span four LABs, three LABs and one M512 RAM block, two LABs and one M4K RAM block, or two LABs and one DSP block to the right or left of a source LAB. These resources are used for fast
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Stratix Architecture
row connections in a four-LAB region. Every LAB has its own set of R4 interconnects to drive either left or right. Figure 2-9 shows R4 interconnect connections from an LAB. R4 interconnects can drive and be driven by DSP blocks and RAM blocks and horizontal IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4 interconnect. For R4 interconnects that drive to the right, the primary LAB and right neighbor can drive on to the interconnect. For R4 interconnects that drive to the left, the primary LAB and its left neighbor can drive on to the interconnect. R4 interconnects can drive other R4 interconnects to extend the range of LABs they can drive. R4 interconnects can also drive C4 and C16 interconnects for connections from one row to another. Additionally, R4 interconnects can drive R24 interconnects. Figure 2-9. R4 Interconnect Connections
Adjacent LAB can Drive onto Another LAB's R4 Interconnect R4 Interconnect Driving Left C4, C8, and C16 Column Interconnects (1) R4 Interconnect Driving Right
LAB Neighbor
Primary LAB (2)
LAB Neighbor
Notes to Figure 2-9:
(1) (2) C4 interconnects can drive R4 interconnects. This pattern is repeated for every LAB in the LAB row.
The R8 interconnects span eight LABs, M512 or M4K RAM blocks, or DSP blocks to the right or left from a source LAB. These resources are used for fast row connections in an eight-LAB region. Every LAB has its own set of R8 interconnects to drive either left or right. R8 interconnect connections between LABs in a row are similar to the R4 connections shown in Figure 2-9, with the exception that they connect to eight LABs to the right or left, not four. Like R4 interconnects, R8 interconnects can drive and be driven by all types of architecture blocks. R8 interconnects
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MultiTrack Interconnect
can drive other R8 interconnects to extend their range as well as C8 interconnects for row-to-row connections. One R8 interconnect is faster than two R4 interconnects connected together. R24 row interconnects span 24 LABs and provide the fastest resource for long row connections between LABs, TriMatrix memory, DSP blocks, and IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row interconnects drive to other row or column interconnects at every fourth LAB and do not drive directly to LAB local interconnects. R24 row interconnects drive LAB local interconnects via R4 and C4 interconnects. R24 interconnects can drive R24, R4, C16, and C4 interconnects. The column interconnect operates similarly to the row interconnect and vertically routes signals to and from LABs, TriMatrix memory, DSP blocks, and IOEs. Each column of LABs is served by a dedicated column interconnect, which vertically routes signals to and from LABs, TriMatrix memory and DSP blocks, and horizontal IOEs. These column resources include:

LUT chain interconnects within an LAB Register chain interconnects within an LAB C4 interconnects traversing a distance of four blocks in up and down direction C8 interconnects traversing a distance of eight blocks in up and down direction C16 column interconnects for high-speed vertical routing through the device
Stratix devices include an enhanced interconnect structure within LABs for routing LE output to LE input connections faster using LUT chain connections and register chain connections. The LUT chain connection allows the combinatorial output of an LE to directly drive the fast input of the LE right below it, bypassing the local interconnect. These resources can be used as a high-speed connection for wide fan-in functions from LE 1 to LE 10 in the same LAB. The register chain connection allows the register output of one LE to connect directly to the register input of the next LE in the LAB for fast shift registers. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. Figure 2-10 shows the LUT chain and register chain interconnects.
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Stratix Architecture
Figure 2-10. LUT Chain & Register Chain Interconnects
Local Interconnect Routing Among LEs in the LAB LUT Chain Routing to Adjacent LE LE 1
Register Chain Routing to Adjacent LE's Register Input
LE 2 Local Interconnect LE 3 LE 4 LE 5 LE 6
LE 7 LE 8 LE 9
LE 10
The C4 interconnects span four LABs, M512, or M4K blocks up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. Figure 2-11 shows the C4 interconnect connections from an LAB in a column. The C4 interconnects can drive and be driven by all types of architecture blocks, including DSP blocks, TriMatrix memory blocks, and vertical IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections.
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MultiTrack Interconnect
Figure 2-11. C4 Interconnect Connections Note (1)
C4 Interconnect Drives Local and R4 Interconnects up to Four Rows
C4 Interconnect Driving Up
LAB
Row Interconnect
Adjacent LAB can drive onto neighboring LAB's C4 interconnect
Local Interconnect
C4 Interconnect Driving Down
Note to Figure 2-11:
(1) Each C4 interconnect can drive either up or down four rows.
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Stratix Architecture
C8 interconnects span eight LABs, M512, or M4K blocks up or down from a source LAB. Every LAB has its own set of C8 interconnects to drive either up or down. C8 interconnect connections between the LABs in a column are similar to the C4 connections shown in Figure 2-11 with the exception that they connect to eight LABs above and below. The C8 interconnects can drive and be driven by all types of architecture blocks similar to C4 interconnects. C8 interconnects can drive each other to extend their range as well as R8 interconnects for column-to-column connections. C8 interconnects are faster than two C4 interconnects. C16 column interconnects span a length of 16 LABs and provide the fastest resource for long column connections between LABs, TriMatrix memory blocks, DSP blocks, and IOEs. C16 interconnects can cross MRAM blocks and also drive to row and column interconnects at every fourth LAB. C16 interconnects drive LAB local interconnects via C4 and R4 interconnects and do not drive LAB local interconnects directly. All embedded blocks communicate with the logic array similar to LABto-LAB interfaces. Each block (i.e., TriMatrix memory and DSP blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks, labclk[7..0].
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MultiTrack Interconnect
Table 2-2 shows the Stratix device's routing scheme.
Table 2-2. Stratix Device Routing Scheme Destination Direct Link Interconnect
Local Interconnect
M512 RAM Block
R24 Interconnect
C16 Interconnect
Register Chain
M-RAM Block
Source LUT Chain
M4K RAM Block
R4 Interconnect
R8 Interconnect
C4 Interconnect
C8 Interconnect
Column IOE v
DSP Blocks
LUT Chain Register Chain Local Interconnect Direct Link Interconnect R4 Interconnect R8 Interconnect R24 Interconnect C4 Interconnect C8 Interconnect C16 Interconnect LE M512 RAM Block M4K RAM Block M-RAM Block DSP Blocks Column IOE Row IOE
v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v
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Row IOE
LE
Stratix Architecture
TriMatrix Memory
TriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM blocks. Although these memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. Table 2-3 shows the size and features of the different RAM blocks.
Table 2-3. TriMatrix Memory Features (Part 1 of 2) Memory Feature
Maximum performance True dual-port memory Simple dual-port memory Single-port memory Shift register ROM FIFO buffer Byte enable Parity bits Mixed clock mode Memory initialization Simple dual-port memory mixed width support True dual-port memory mixed width support Power-up conditions Register clears Mixed-port readduring-write Outputs cleared Input and output registers Unknown output/old data
M512 RAM Block M4K RAM Block (32 x 18 Bits) (128 x 36 Bits)
(1) (1)
M-RAM Block (4K x 144 Bits)
(1)
v v v v v v v v v v v v v v v v v v v v v
Outputs cleared Input and output registers Unknown output/old data
v v v
(2)
v v v v
v v
Outputs unknown Output registers Unknown output
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TriMatrix Memory
Table 2-3. TriMatrix Memory Features (Part 2 of 2) Memory Feature
Configurations
M512 RAM Block M4K RAM Block (32 x 18 Bits) (128 x 36 Bits)
512 x 1 256 x 2 128 x 4 64 x 8 64 x 9 32 x 16 32 x 18 4K x 1 2K x 2 1K x 4 512 x 8 512 x 9 256 x 16 256 x 18 128 x 32 128 x 36
M-RAM Block (4K x 144 Bits)
64K x 8 64K x 9 32K x 16 32K x 18 16K x 32 16K x 36 8K x 64 8K x 72 4K x 128 4K x 144
Notes to Table 2-3:
(1) (2) See Table 4-36 for maximum performance information. The M-RAM block does not support memory initializations. However, the M-RAM block can emulate a ROM function using a dual-port RAM bock. The Stratix device must write to the dual-port memory once and then disable the write-enable ports afterwards.
1
Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations.
Memory Modes
TriMatrix memory blocks include input registers that synchronize writes and output registers to pipeline designs and improve system performance. M4K and M-RAM memory blocks offer a true dual-port mode to support any combination of two-port operations: two reads, two writes, or one read and one write at two different clock frequencies. Figure 2-12 shows true dual-port memory. Figure 2-12. True Dual-Port Memory Configuration
A dataA[ ] addressA[ ] wrenA clockA clockenA qA[ ] aclrA B dataB[ ] addressB[ ] wrenB clockB clockenB qB[ ] aclrB
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Stratix Architecture
In addition to true dual-port memory, the memory blocks support simple dual-port and single-port RAM. Simple dual-port memory supports a simultaneous read and write and can either read old data before the write occurs or just read the don't care bits. Single-port memory supports nonsimultaneous reads and writes, but the q[] port will output the data once it has been written to the memory (if the outputs are not registered) or after the next rising edge of the clock (if the outputs are registered). For more information, see Chapter 2, TriMatrix Embedded Memory Blocks in Stratix & Stratix GX Devices of the Stratix Device Handbook, Volume 2. Figure 2-13 shows these different RAM memory port configurations for TriMatrix memory. Figure 2-13. Simple Dual-Port & Single-Port Memory Configurations
Simple Dual-Port Memory
data[ ] wraddress[ ] wren inclock inclocken inaclr rdaddress[ ] rden q[ ] outclock outclocken outaclr
Single-Port Memory (1)
data[ ] address[ ] wren inclock inclocken inaclr
q[ ] outclock outclocken outaclr
Note to Figure 2-13:
(1) Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size.
The memory blocks also enable mixed-width data ports for reading and writing to the RAM ports in dual-port RAM configuration. For example, the memory block can be written in x1 mode at port A and read out in x16 mode from port B.
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TriMatrix Memory
TriMatrix memory architecture can implement pipelined RAM by registering both the input and output signals to the RAM block. All TriMatrix memory block inputs are registered providing synchronous write cycles. In synchronous operation, the memory block generates its own self-timed strobe write enable (WREN) signal derived from the global or regional clock. In contrast, a circuit using asynchronous RAM must generate the RAM WREN signal while ensuring its data and address signals meet setup and hold time specifications relative to the WREN signal. The output registers can be bypassed. Flow-through reading is possible in the simple dual-port mode of M512 and M4K RAM blocks by clocking the read enable and read address registers on the negative clock edge and bypassing the output registers. Two single-port memory blocks can be implemented in a single M4K block as long as each of the two independent block sizes is equal to or less than half of the M4K block size. The Quartus II software automatically implements larger memory by combining multiple TriMatrix memory blocks. For example, two 256 x 16-bit RAM blocks can be combined to form a 256 x 32-bit RAM block. Memory performance does not degrade for memory blocks using the maximum number of words available in one memory block. Logical memory blocks using less than the maximum number of words use physical blocks in parallel, eliminating any external control logic that would increase delays. To create a larger high-speed memory block, the Quartus II software automatically combines memory blocks with LE control logic.
Clear Signals
When applied to input registers, the asynchronous clear signal for the TriMatrix embedded memory immediately clears the input registers. However, the output of the memory block does not show the effects until the next clock edge. When applied to output registers, the asynchronous clear signal clears the output registers and the effects are seen immediately.
Parity Bit Support
The memory blocks support a parity bit for each byte. The parity bit, along with internal LE logic, can implement parity checking for error detection to ensure data integrity. You can also use parity-size data words to store user-specified control bits. In the M4K and M-RAM blocks, byte enables are also available for data input masking during write operations.
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Stratix Architecture
Shift Register Support
You can configure embedded memory blocks to implement shift registers for DSP applications such as pseudo-random number generators, multichannel filtering, auto-correlation, and cross-correlation functions. These and other DSP applications require local data storage, traditionally implemented with standard flip-flops, which can quickly consume many logic cells and routing resources for large shift registers. A more efficient alternative is to use embedded memory as a shift register block, which saves logic cell and routing resources and provides a more efficient implementation with the dedicated circuitry. The size of a w x m x n shift register is determined by the input data width (w), the length of the taps (m), and the number of taps (n). The size of a w x m x n shift register must be less than or equal to the maximum number of memory bits in the respective block: 576 bits for the M512 RAM block and 4,608 bits for the M4K RAM block. The total number of shift register outputs (number of taps n x width w) must be less than the maximum data width of the RAM block (18 for M512 blocks, 36 for M4K blocks). To create larger shift registers, the memory blocks are cascaded together. Data is written into each address location at the falling edge of the clock and read from the address at the rising edge of the clock. The shift register mode logic automatically controls the positive and negative edge clocking to shift the data in one clock cycle. Figure 2-14 shows the TriMatrix memory block in the shift register mode.
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TriMatrix Memory
Figure 2-14. Shift Register Memory Configuration
w x m x n Shift Register m-Bit Shift Register w w
m-Bit Shift Register w w
n Number of Taps
m-Bit Shift Register w w
m-Bit Shift Register w w
Memory Block Size
TriMatrix memory provides three different memory sizes for efficient application support. The large number of M512 blocks are ideal for designs with many shallow first-in first-out (FIFO) buffers. M4K blocks provide additional resources for channelized functions that do not require large amounts of storage. The M-RAM blocks provide a large single block of RAM ideal for data packet storage. The different-sized blocks allow Stratix devices to efficiently support variable-sized memory in designs. The Quartus II software automatically partitions the user-defined memory into the embedded memory blocks using the most efficient size combinations. You can also manually assign the memory to a specific block size or a mixture of block sizes.
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M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful for implementing small FIFO buffers, DSP, and clock domain transfer applications. Each block contains 576 RAM bits (including parity bits). M512 RAM blocks can be configured in the following modes:

Simple dual-port RAM Single-port RAM FIFO ROM Shift register
When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents. The memory address depths and output widths can be configured as 512 x 1, 256 x 2, 128 x 4, 64 x 8 (64 x 9 bits with parity), and 32 x 16 (32 x 18 bits with parity). Mixed-width configurations are also possible, allowing different read and write widths. Table 2-4 summarizes the possible M512 RAM block configurations.
Table 2-4. M512 RAM Block Configurations (Simple Dual-Port RAM) Write Port Read Port 512 x 1
512 x 1 256 x 2 128 x 4 64 x 8 32 x 16 64 x 9 32 x 18
256 x 2 v v v v v
128 x 4 v v v
64 x 8 v v v
32 x 16 v v v v
64 x 9
32 x 18
v v v v v
v
v v
When the M512 RAM block is configured as a shift register block, a shift register of size up to 576 bits is possible. The M512 RAM block can also be configured to support serializer and deserializer applications. By using the mixed-width support in combination with DDR I/O standards, the block can function as a SERDES to support low-speed serial I/O standards using global or regional clocks. See "I/O Structure" on page 2-104 for details on dedicated SERDES in Stratix devices.
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TriMatrix Memory
M512 RAM blocks can have different clocks on its inputs and outputs. The wren, datain, and write address registers are all clocked together from one of the two clocks feeding the block. The read address, rden, and output registers can be clocked by either of the two clocks driving the block. This allows the RAM block to operate in read/write or input/output clock modes. Only the output register can be bypassed. The eight labclk signals or local interconnect can drive the inclock, outclock, wren, rden, inclr, and outclr signals. Because of the advanced interconnect between the LAB and M512 RAM blocks, LEs can also control the wren and rden signals and the RAM clock, clock enable, and asynchronous clear signals. Figure 2-15 shows the M512 RAM block control signal generation logic. The RAM blocks within Stratix devices have local interconnects to allow LEs and interconnects to drive into RAM blocks. The M512 RAM block local interconnect is driven by the R4, R8, C4, C8, and direct link interconnects from adjacent LABs. The M512 RAM blocks can communicate with LABs on either the left or right side through these row interconnects or with LAB columns on the left or right side with the column interconnects. Up to 10 direct link input connections to the M512 RAM block are possible from the left adjacent LABs and another 10 possible from the right adjacent LAB. M512 RAM outputs can also connect to left and right LABs through 10 direct link interconnects. The M512 RAM block has equal opportunity for access and performance to and from LABs on either its left or right side. Figure 2-16 shows the M512 RAM block to logic array interface.
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Figure 2-15. M512 RAM Block Control Signals
Dedicated Row LAB Clocks Local Interconnect 8
Local Interconnect
Local Interconnect Local Interconnect
Local Interconnect Local Interconnect Local Interconnect Local Interconnect inclock
inclocken
outclocken
wren
outclr
outclock
rden
inclr
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Figure 2-16. M512 RAM Block LAB Row Interface
C4 and C8 Interconnects R4 and R8 Interconnects 10
Direct link interconnect to adjacent LAB
Direct link interconnect to adjacent LAB dataout
Direct link interconnect from adjacent LAB
M512 RAM Block
Direct link interconnect from adjacent LAB
Control Signals datain address Clocks 2 8 Small RAM Block Local Interconnect Region LAB Row Clocks
M4K RAM Blocks
The M4K RAM block includes support for true dual-port RAM. The M4K RAM block is used to implement buffers for a wide variety of applications such as storing processor code, implementing lookup schemes, and implementing larger memory applications. Each block contains 4,608 RAM bits (including parity bits). M4K RAM blocks can be configured in the following modes:

True dual-port RAM Simple dual-port RAM Single-port RAM FIFO ROM Shift register
When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents.
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Stratix Architecture
The memory address depths and output widths can be configured as 4,096 x 1, 2,048 x 2, 1,024 x 4, 512 x 8 (or 512 x 9 bits), 256 x 16 (or 256 x 18 bits), and 128 x 32 (or 128 x 36 bits). The 128 x 32- or 36-bit configuration is not available in the true dual-port mode. Mixed-width configurations are also possible, allowing different read and write widths. Tables 2-5 and 2-6 summarize the possible M4K RAM block configurations.
Table 2-5. M4K RAM Block Configurations (Simple Dual-Port) Write Port Read Port 4K x 1
4K x 1 2K x 2 1K x 4 512 x 8 256 x 16 128 x 32 512 x 9 256 x 18 128 x 36
2K x 2 v v v v v v
1K x 4 512 x 8 256 x 16 v v v v v v v v v v v v v v v v v v
128 x 32 512 x 9 256 x 18 v v v v v v v v v v v v
128 x 36
v v v v v v
v v v
Table 2-6. M4K RAM Block Configurations (True Dual-Port) Port B Port A 4K x 1
4K x 1 2K x 2 1K x 4 512 x 8 256 x 16 512 x 9 256 x 18
2K x 2 v v v v v
1K x 4 v v v v v
512 x 8 v v v v v
256 x 16 v v v v v
512 x 9
256 x 18
v v v v v
v v
v v
When the M4K RAM block is configured as a shift register block, you can create a shift register up to 4,608 bits (w x m x n).
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M4K RAM blocks support byte writes when the write port has a data width of 16, 18, 32, or 36 bits. The byte enables allow the input data to be masked so the device can write to specific bytes. The unwritten bytes retain the previous written value. Table 2-7 summarizes the byte selection.
Table 2-7. Byte Enable for M4K Blocks Notes (1), (2) byteena[3..0]
[0] = 1 [1] = 1 [2] = 1 [3] = 1 Notes to Table 2-7:
(1) (2) Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, i.e., in x 16 and x 32 modes.
datain x18
[8..0] [17..9] - -
datain x36
[8..0] [17..9] [26..18] [35..27]
The M4K RAM blocks allow for different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M4K RAM block registers (renwe, address, byte enable, datain, and output registers). Only the output register can be bypassed. The eight labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K RAM block. LEs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in Figure 2-17. The R4, R8, C4, C8, and direct link interconnects from adjacent LABs drive the M4K RAM block local interconnect. The M4K RAM blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 10 direct link input connections to the M4K RAM Block are possible from the left adjacent LABs and another 10 possible from the right adjacent LAB. M4K RAM block outputs can also connect to left and right LABs through 10 direct link interconnects each. Figure 2-18 shows the M4K RAM block to logic array interface.
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Stratix Architecture
Figure 2-17. M4K RAM Block Control Signals
Dedicated Row LAB Clocks Local Interconnect 8
Local Interconnect
Local Interconnect Local Interconnect Local Interconnect clocken_a Local Interconnect clock_a renwe_a alcr_b clocken_b alcr_a renwe_b clock_b
Local Interconnect Local Interconnect Local Interconnect Local Interconnect
Figure 2-18. M4K RAM Block LAB Row Interface
C4 and C8 Interconnects R4 and R8 Interconnects
Direct link interconnect to adjacent LAB
10
Direct link interconnect to adjacent LAB dataout
Direct link interconnect from adjacent LAB
M4K RAM Block Byte enable Control Signals Clocks
Direct link interconnect from adjacent LAB
address
datain
8 M4K RAM Block Local Interconnect Region LAB Row Clocks
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TriMatrix Memory
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for applications where a large volume of data must be stored on-chip. Each block contains 589,824 RAM bits (including parity bits). The M-RAM block can be configured in the following modes:

True dual-port RAM Simple dual-port RAM Single-port RAM FIFO RAM
You cannot use an initialization file to initialize the contents of a M-RAM block. All M-RAM block contents power up to an undefined value. Only synchronous operation is supported in the M-RAM block, so all inputs are registered. Output registers can be bypassed. The memory address and output width can be configured as 64K x 8 (or 64K x 9 bits), 32K x 16 (or 32K x 18 bits), 16K x 32 (or 16K x 36 bits), 8K x 64 (or 8K x 72 bits), and 4K x 128 (or 4K x 144 bits). The 4K x 128 configuration is unavailable in true dual-port mode because there are a total of 144 data output drivers in the block. Mixed-width configurations are also possible, allowing different read and write widths. Tables 2-8 and 2-9 summarize the possible M-RAM block configurations:
Table 2-8. M-RAM Block Configurations (Simple Dual-Port) Write Port Read Port 64K x 9
64K x 9 32K x 18 16K x 36 8K x 72 4K x 144
32K x 18 v v v v
16K x 36 v v v v
8K x 72 v v v v
4K x 144
v v v v
v
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Table 2-9. M-RAM Block Configurations (True Dual-Port) Port B Port A 64K x 9
64K x 9 32K x 18 16K x 36 8K x 72
32K x 18 v v v v
16K x 36 v v v v
8K x 72 v v v v
v v v v
The read and write operation of the memory is controlled by the WREN signal, which sets the ports into either read or write modes. There is no separate read enable (RE) signal. Writing into RAM is controlled by both the WREN and byte enable (byteena) signals for each port. The default value for the byteena signal is high, in which case writing is controlled only by the WREN signal. The byte enables are available for the x18, x36, and x72 modes. In the x144 simple dual-port mode, the two sets of byteena signals (byteena_a and byteena_b) are combined to form the necessary 16 byte enables. Tables 2-10 and 2-11 summarize the byte selection.
Table 2-10. Byte Enable for M-RAM Blocks Notes (1), (2) byteena[3..0]
[0] = 1 [1] = 1 [2] = 1 [3] = 1 [4] = 1 [5] = 1 [6] = 1 [7] = 1
datain x18
[8..0] [17..9] - - - - - -
datain x36
[8..0] [17..9] [26..18] [35..27] - - - -
datain x72
[8..0] [17..9] [26..18] [35..27] [44..36] [53..45] [62..54] [71..63]
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Table 2-11. M-RAM Combined Byte Selection for x144 Mode Notes (1), (2) byteena[15..0]
[0] = 1 [1] = 1 [2] = 1 [3] = 1 [4] = 1 [5] = 1 [6] = 1 [7] = 1 [8] = 1 [9] = 1 [10] = 1 [11] = 1 [12] = 1 [13] = 1 [14] = 1 [15] = 1 Notes to Tables 2-10 and 2-11:
(1) (2) Any combination of byte enables is possible. Byte enables can be used in the same manner with 8-bit words, i.e., in x 16, x 32, x 64, and x 128 modes.
datain x144
[8..0] [17..9] [26..18] [35..27] [44..36] [53..45] [62..54] [71..63] [80..72] [89..81] [98..90] [107..99] [116..108] [125..117] [134..126] [143..135]
Similar to all RAM blocks, M-RAM blocks can have different clocks on their inputs and outputs. All input registers--renwe, datain, address, and byte enable registers--are clocked together from either of the two clocks feeding the block. The output register can be bypassed. The eight labclk signals or local interconnect can drive the control signals for the A and B ports of the M-RAM block. LEs can also control the clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals as shown in Figure 2-19.
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Figure 2-19. M-RAM Block Control Signals
Dedicated Row LAB Clocks Local Interconnect Local Interconnect 8
Local Interconnect
Local Interconnect Local Interconnect
Local Interconnect Local Interconnect Local Interconnect
clocken_a
clocken_b
aclr_b
renwe_b
clock_a
clock_b
aclr_a
renwe_a
One of the M-RAM block's horizontal sides drive the address and control signal (clock, renwe, byteena, etc.) inputs. Typically, the horizontal side closest to the device perimeter contains the interfaces. The one exception is when two M-RAM blocks are paired next to each other. In this case, the side of the M-RAM block opposite the common side of the two blocks contains the input interface. The top and bottom sides of any M-RAM block contain data input and output interfaces to the logic array. The top side has 72 data inputs and 72 data outputs for port B, and the bottom side has another 72 data inputs and 72 data outputs for port A. Figure 2-20 shows an example floorplan for the EP1S60 device and the location of the M-RAM interfaces.
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TriMatrix Memory
Figure 2-20. EP1S60 Device with M-RAM Interface Locations Note (1)
M-RAM pairs interface to top, bottom, and side opposite of block-to-block border. Independent M-RAM blocks interface to top, bottom, and side facing device perimeter for easy access to horizontal I/O pins.
M-RAM Block
M-RAM Block
M-RAM Block
M-RAM Block
M-RAM Block
M-RAM Block
DSP Blocks
M512 Blocks
M4K Blocks
LABs
DSP Blocks
Note to Figure 2-20:
(1) Device shown is an EP1S60 device. The number and position of M-RAM blocks varies in other devices.
The M-RAM block local interconnect is driven by the R4, R8, C4, C8, and direct link interconnects from adjacent LABs. For independent M-RAM blocks, up to 10 direct link address and control signal input connections to the M-RAM block are possible from the left adjacent LABs for M-RAM
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blocks facing to the left, and another 10 possible from the right adjacent LABs for M-RAM blocks facing to the right. For column interfacing, every M-RAM column unit connects to the right and left column lines, allowing each M-RAM column unit to communicate directly with three columns of LABs. Figures 2-21 through 2-23 show the interface between the M-RAM block and the logic array.
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TriMatrix Memory
Figure 2-21. Left-Facing M-RAM to Interconnect Interface Notes (1), (2)
M512 RAM Block Columns
Row Unit Interface Allows LAB Rows to Drive Address and Control Signals to M-RAM Block
LABs in Column M-RAM Boundary
Column Interface Block Drives to and from C4 and C8 Interconnects
B1 B2 B3 Port B B4 B5 B6
R11 R10 R9 R8 R7 R6 M-RAM Block
R5 R4 R3 R2
R1 A1 A2
Port A A3 A4 A5 A6
Column Interface Block Allows LAB Columns to Drive datain and dataout to and from M-RAM Block
LABs in Row M-RAM Boundary
LAB Interface Blocks
Notes to Figure 2-21:
(1) (2) Only R24 and C16 interconnects cross the M-RAM block boundaries. The right-facing M-RAM block has interface blocks on the right side, but none on the left. B1 to B6 and A1 to A6 orientation is clipped across the vertical axis for right-facing M-RAM blocks.
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Figure 2-22. M-RAM Row Unit Interface to Interconnect
C4 and C8 Interconnects R4 and R8 Interconnects M-RAM Block
LAB
10
Direct Link Interconnects addressa addressb renwe_a renwe_b byteenaA[ ] byteenaB[ ] clocken_a clocken_b clock_a clock_b aclr_a aclr_b
Up to 24
Row Interface Block M-RAM Block to LAB Row Interface Block Interconnect Region
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Figure 2-23. M-RAM Column Unit Interface to Interconnect
C4 and C8 Interconnects
LAB
LAB
LAB
M-RAM Block to LAB Row Interface Block Interconnect Region Column Interface Block
12 datain
12 dataout
M-RAM Block
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Table 2-12 shows the input and output data signal connections for the column units (B1 to B6 and A1 to A6). It also shows the address and control signal input connections to the row units (R1 to R11).
Table 2-12. M-RAM Row & Column Interface Unit Signals Unit Interface Block
R1 R2 R3 R4 R5 R6
Input SIgnals
addressa[7..0] addressa[15..8] byte_enable_a[7..0] renwe_a clock_a clocken_a clock_b clocken_b byte_enable_b[7..0] renwe_b addressb[15..8] addressb[7..0] datain_b[71..60] datain_b[59..48] datain_b[47..36] datain_b[35..24] datain_b[23..12] datain_b[11..0] datain_a[71..60] datain_a[59..48] datain_a[47..36] datain_a[35..24] datain_a[23..12] datain_a[11..0]
Output Signals
R7 R8 R9 R10 R11 B1 B2 B3 B4 B5 B6 A1 A2 A3 A4 A5 A6
dataout_b[71..60] dataout_b[59..48] dataout_b[47..36] dataout_b[35..24] dataout_b[23..12] dataout_b[11..0] dataout_a[71..60] dataout_a[59..48] dataout_a[47..36] dataout_a[35..24] dataout_a[23..12] dataout_a[11..0]
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TriMatrix Memory
Independent Clock Mode
The memory blocks implement independent clock mode for true dualport memory. In this mode, a separate clock is available for each port (ports A and B). Clock A controls all registers on the port A side, while clock B controls all registers on the port B side. Each port, A and B, also supports independent clock enables and asynchronous clear signals for port A and B registers. Figure 2-24 shows a TriMatrix memory block in independent clock mode.
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8 LAB Row Clocks A 8
D ENA Q
(1) (2)
B Data In Data In
Q D ENA
Notes to Figure 2-24
Memory Block 256 16 (2) 512 8 1,024 4 2,048 2 4,096 1
D ENA Q
8 dataB[ ]
dataA[ ]
byteenaA[ ] Byte Enable A
Byte Enable B
Q
D ENA
byteenaB[ ]
addressA[ ]
D ENA Q
Address A
Address B
Q
D ENA
addressB[ ]
wrenA
wrenB
Figure 2-24. Independent Clock Mode Notes (1), (2)
clkenA
ENA
D
Q
clockA
Write Pulse Generator
Write/Read Enable
Write/Read Enable
Q
D ENA
Write Pulse Generator Data Out Data Out
clkenB clockB
D ENA
Q
Q
D ENA
All registers shown have asynchronous clear ports. Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations.
qA[ ] qB[ ]
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TriMatrix Memory
Input/Output Clock Mode
Input/output clock mode can be implemented for both the true and simple dual-port memory modes. On each of the two ports, A or B, one clock controls all registers for inputs into the memory block: data input, wren, and address. The other clock controls the block's data output registers. Each memory block port, A or B, also supports independent clock enables and asynchronous clear signals for input and output registers. Figures 2-25 and 2-26 show the memory block in input/output clock mode.
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8 LAB Row Clocks 8 A
D ENA Q
(1) (2)
B Data In
Q D ENA
8 dataB[ ]
Notes to Figure 2-25:
Data In Memory Block 256 x 16 (2) 512 x 8 1,024 x 4 2,048 x 2 4,096 x 1 Byte Enable B
D ENA Q
dataA[ ]
byteenaA[ ] Byte Enable A
Q
D ENA
byteenaB[ ]
addressA[ ]
D ENA Q
Address A
Address B
Q
D ENA
addressB[ ]
wrenA wrenB
D ENA Q
clkenA
clockA
Write Pulse Generator Data Out
Write/Read Enable
Write/Read Enable
Q
D ENA
Write Pulse Generator Data Out
clkenB
D ENA Q Q D ENA
clockB qA[ ] qB[ ]
Figure 2-25. Input/Output Clock Mode in True Dual-Port Mode Notes (1), (2)
All registers shown have asynchronous clear ports. Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations.
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Figure 2-26. Input/Output Clock Mode in Simple Dual-Port Mode Notes (1), (2)
8 LAB Row Clocks 8 data[ ] D Q ENA Memory Block 256 16 Data In 512 8 1,024 4 2,048 2 4,096 1 Read Address
address[ ]
D Q ENA
Data Out byteena[ ] D Q ENA Byte Enable
D Q ENA
To MultiTrack Interconnect
wraddress[ ]
D Q ENA
Write Address
rden D Q ENA wren Read Enable
outclken
inclken wrclock
D Q ENA
Write Pulse Generator
Write Enable
rdclock
Notes to Figure 2-26:
(1) (2) All registers shown except the rden register have asynchronous clear ports. Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations.
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Stratix Architecture
Read/Write Clock Mode
The memory blocks implement read/write clock mode for simple dualport memory. You can use up to two clocks in this mode. The write clock controls the block's data inputs, wraddress, and wren. The read clock controls the data output, rdaddress, and rden. The memory blocks support independent clock enables for each clock and asynchronous clear signals for the read- and write-side registers. Figure 2-27 shows a memory block in read/write clock mode.
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TriMatrix Memory
Figure 2-27. Read/Write Clock Mode in Simple Dual-Port Mode Notes (1), (2)
8 LAB Row Clocks 8 data[ ] D Q ENA Memory Block 256 x 16 512 x 8 1,024 x 4 Data In 2,048 x 2 4,096 x 1 Data Out address[ ] D Q ENA Read Address D Q ENA To MultiTrack Interconnect
wraddress[ ]
D Q ENA
Write Address
byteena[ ]
D Q ENA
Byte Enable
rden D Q ENA wren Read Enable
outclken
inclken wrclock
D Q ENA
Write Pulse Generator
Write Enable
rdclock
Notes to Figure 2-27:
(1) (2) All registers shown except the rden register have asynchronous clear ports. Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations.
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Stratix Architecture
Single-Port Mode
The memory blocks also support single-port mode, used when simultaneous reads and writes are not required. See Figure 2-28. A single block in a memory block can support up to two single-port mode RAM blocks in the M4K RAM blocks if each RAM block is less than or equal to 2K bits in size. Figure 2-28. Single-Port Mode Note (1)
8 LAB Row Clocks
8 data[ ] D Q ENA
RAM/ROM 256 x 16 512 x 8 1,024 x 4 Data In 2,048 x 2 4,096 x 1 Data Out D Q ENA
To MultiTrack Interconnect
address[ ]
D Q ENA
Address
wren
Write Enable outclken
inclken inclock
D Q ENA
Write Pulse Generator
outclock
Note to Figure 2-28:
(1) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both read and write operations.
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Digital Signal Processing Block
Digital Signal Processing Block
The most commonly used DSP functions are finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, direct cosine transform (DCT) functions, and correlators. All of these blocks have the same fundamental building block: the multiplier. Additionally, some applications need specialized operations such as multiply-add and multiply-accumulate operations. Stratix devices provide DSP blocks to meet the arithmetic requirements of these functions. Each Stratix device has two columns of DSP blocks to efficiently implement DSP functions faster than LE-based implementations. Larger Stratix devices have more DSP blocks per column (see Table 2-13). Each DSP block can be configured to support up to:

Eight 9 x 9-bit multipliers Four 18 x 18-bit multipliers One 36 x 36-bit multiplier
As indicated, the Stratix DSP block can support one 36 x 36-bit multiplier in a single DSP block. This is true for any matched sign multiplications (either unsigned by unsigned or signed by signed), but the capabilities for dynamic and mixed sign multiplications are handled differently. The following list provides the largest functions that can fit into a single DSP block.

36 x 36-bit unsigned by unsigned multiplication 36 x 36-bit signed by signed multiplication 35 x 36-bit unsigned by signed multiplication 36 x 35-bit signed by unsigned multiplication 36 x 35-bit signed by dynamic sign multiplication 35 x 36-bit dynamic sign by signed multiplication 35 x 36-bit unsigned by dynamic sign multiplication 36 x 35-bit dynamic sign by unsigned multiplication 35 x 35-bit dynamic sign multiplication when the sign controls for each operand are different 36 x 36-bit dynamic sign multiplication when the same sign control is used for both operands This list only shows functions that can fit into a single DSP block. Multiple DSP blocks can support larger multiplication functions.
1
Figure 2-29 shows one of the columns with surrounding LAB rows.
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Stratix Architecture
Figure 2-29. DSP Blocks Arranged in Columns
DSP Block Column
8 LAB Rows
DSP Block
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Table 2-13 shows the number of DSP blocks in each Stratix device.
Table 2-13. DSP Blocks in Stratix Devices Notes (1), (2) Device
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 Notes to Table 2-13:
(1)
DSP Blocks
6 10 10 12 14 18 22
Total 9 x 9 Multipliers
48 80 80 96 112 144 176
Total 18 x 18 Multipliers
24 40 40 48 56 72 88
Total 36 x 36 Multipliers
6 10 10 12 14 18 22
(2)
Each device has either the number of 9 x 9-, 18 x 18-, or 36 x 36-bit multipliers shown. The total number of multipliers for each device is not the sum of all the multipliers. The number of supported multiply functions shown is based on signed/signed or unsigned/unsigned implementations.
DSP block multipliers can optionally feed an adder/subtractor or accumulator within the block depending on the configuration. This makes routing to LEs easier, saves LE routing resources, and increases performance, because all connections and blocks are within the DSP block. Additionally, the DSP block input registers can efficiently implement shift registers for FIR filter applications. Figure 2-30 shows the top-level diagram of the DSP block configured for 18 x 18-bit multiplier mode. Figure 2-31 shows the 9 x 9-bit multiplier configuration of the DSP block.
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Stratix Architecture
Figure 2-30. DSP Block Diagram for 18 x 18-Bit Configuration
Optional Serial Shift Register Inputs from Previous DSP Block
Multiplier Stage Optional Stage Configurable as Accumulator or Dynamic Adder/Subtractor
D Q
D
Q
Output Selection Multiplexer
ENA CLRN
D
Q
ENA CLRN
ENA CLRN
Adder/ Subtractor/ Accumulator 1
D
Q
ENA CLRN
D
Q
D
Q
ENA CLRN
ENA CLRN
Summation
D
Q
ENA CLRN
D
Q
D
Q
ENA CLRN
Summation Stage for Adding Four Multipliers Together
Optional Output Register Stage
ENA CLRN
Adder/ Subtractor/ Accumulator 2
D
Q
Optional Serial Shift Register Outputs to Next DSP Block in the Column
ENA CLRN
D
Q
D
Q
ENA CLRN
Optional Pipeline Register Stage
ENA CLRN
Optional Input Register Stage with Parallel Input or Shift Register Configuration
to MultiTrack Interconnect
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Digital Signal Processing Block
Figure 2-31. DSP Block Diagram for 9 x 9-Bit Configuration
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Adder/ Subtractor/ 1a
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Summation
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Adder/ Subtractor/ 1b
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Output Selection Multiplexer
D Q ENA CLRN
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Adder/ Subtractor/ 2a
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Summation
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
Adder/ Subtractor/ 2b
D Q ENA CLRN D Q ENA CLRN
D Q ENA CLRN
To MultiTrack Interconnect
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Stratix Architecture
The DSP block consists of the following elements:

Multiplier block Adder/output block
Multiplier Block
The DSP block multiplier block consists of the input registers, a multiplier, and pipeline register for pipelining multiply-accumulate and multiply-add/subtract functions as shown in Figure 2-32. Figure 2-32. Multiplier Sub-Block within Stratix DSP Block
sign_a (1) sign_b (1) aclr[3..0] clock[3..0] ena[3..0]
shiftin B
shiftin A
Data A
D ENA
Q D ENA Q
Result to Adder blocks Optional Multiply-Accumulate and Multiply-Add Pipeline
CLRN
CLRN
Data B
D ENA
Q
CLRN
shiftout B
shiftout A
Note to Figure 2-32:
(1) These signals can be unregistered or registered once to match data path pipelines if required.
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Input Registers
A bank of optional input registers is located at the input of each multiplier and multiplicand inputs to the multiplier. When these registers are configured for parallel data inputs, they are driven by regular routing resources. You can use a clock signal, asynchronous clear signal, and a clock enable signal to independently control each set of A and B inputs for each multiplier in the DSP block. You select these control signals from a set of four different clock[3..0], aclr[3..0], and ena[3..0] signals that drive the entire DSP block. You can also configure the input registers for a shift register application. In this case, the input registers feed the multiplier and drive two dedicated shift output lines: shiftoutA and shiftoutB. The shift outputs of one multiplier block directly feed the adjacent multiplier block in the same DSP block (or the next DSP block) as shown in Figure 2-33, to form a shift register chain. This chain can terminate in any block, that is, you can create any length of shift register chain up to 224 registers. You can use the input shift registers for FIR filter applications. One set of shift inputs can provide data for a filter, and the other are coefficients that are optionally loaded in serial or parallel. When implementing 9 x 9- and 18 x 18-bit multipliers, you do not need to implement external shift registers in LAB LEs. You implement all the filter circuitry within the DSP block and its routing resources, saving LE and general routing resources for general logic. External registers are needed for shift register inputs when using 36 x 36-bit multipliers.
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Stratix Architecture
Figure 2-33. Multiplier Sub-Blocks Using Input Shift Register Connections Note (1)
Data A
D ENA Q
A[n] x B[n]
CLRN D ENA Q
Data B
D ENA
Q
CLRN
CLRN
Data B
Data A
D ENA
Q
A[n 1] x B[n 1]
CLRN D ENA Q
D ENA
Q
CLRN
CLRN
Data B
Data A
D ENA
Q
A[n 2] x B[n 2]
CLRN D ENA Q
D ENA
Q
CLRN
CLRN
Note to Figure 2-33:
(1) Either Data A or Data B input can be set to a parallel input for constant coefficient multiplication.
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Table 2-14 shows the summary of input register modes for the DSP block.
Table 2-14. Input Register Modes Register Input Mode
Parallel input Shift register input
9x9 v v
18 x 18 v v
36 x 36 v
Multiplier
The multiplier supports 9 x 9-, 18 x 18-, or 36 x 36-bit multiplication. Each DSP block supports eight possible 9 x 9-bit or smaller multipliers. There are four multiplier blocks available for multipliers larger than 9 x 9 bits but smaller than 18 x 18 bits. There is one multiplier block available for multipliers larger than 18 x 18 bits but smaller than or equal to 36 x 36 bits. The ability to have several small multipliers is useful in applications such as video processing. Large multipliers greater than 18 x 18 bits are useful for applications such as the mantissa multiplication of a singleprecision floating-point number. The multiplier operands can be signed or unsigned numbers, where the result is signed if either input is signed as shown in Table 2-15. The sign_a and sign_b signals provide dynamic control of each operand's representation: a logic 1 indicates the operand is a signed number, a logic 0 indicates the operand is an unsigned number. These sign signals affect all multipliers and adders within a single DSP block and you can register them to match the data path pipeline. The multipliers are full precision (that is, 18 bits for the 18-bit multiply, 36-bits for the 36-bit multiply, and so on) regardless of whether sign_a or sign_b set the operands as signed or unsigned numbers.
Table 2-15. Multiplier Signed Representation Data A
Unsigned Unsigned Signed Signed
Data B
Unsigned Signed Unsigned Signed
Result
Unsigned Signed Signed Signed
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Stratix Architecture
Pipeline/Post Multiply Register
The output of 9 x 9- or 18 x 18-bit multipliers can optionally feed a register to pipeline multiply-accumulate and multiply-add/subtract functions. For 36 x 36-bit multipliers, this register will pipeline the multiplier function.
Adder/Output Blocks
The result of the multiplier sub-blocks are sent to the adder/output block which consist of an adder/subtractor/accumulator unit, summation unit, output select multiplexer, and output registers. The results are used to configure the adder/output block as a pure output, accumulator, a simple two-multiplier adder, four-multiplier adder, or final stage of the 36-bit multiplier. You can configure the adder/output block to use output registers in any mode, and must use output registers for the accumulator. The system cannot use adder/output blocks independently of the multiplier. Figure 2-34 shows the adder and output stages.
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Figure 2-34. Adder/Output Blocks Note (1)
Accumulator Feedback accum_sload0 (2) Result A
addnsub1 (2)
Adder/ Subtractor/ Accumulator1
overflow0
Output Selection Multiplexer
Result B signa (2)
Summation signb (2)
Output Register Block
Result C
addnsub3 (2)
Adder/ Subtractor/ Accumulator2 overflow1
Result D accum_sload1 (2)
Accumulator Feedback
Notes to Figure 2-34:
(1) (2)
Adder/output block shown in Figure 2-34 is in 18 x 18-bit mode. In 9 x 9-bit mode, there are four adder/subtractor blocks and two summation blocks. These signals are either not registered, registered once, or registered twice to match the data path pipeline.
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Stratix Architecture
Adder/Subtractor/Accumulator
The adder/subtractor/accumulator is the first level of the adder/output block and can be used as an accumulator or as an adder/subtractor. Adder/Subtractor Each adder/subtractor/accumulator block can perform addition or subtraction using the addnsub independent control signal for each firstlevel adder in 18 x 18-bit mode. There are two addnsub[1..0] signals available in a DSP block for any configuration. For 9 x 9-bit mode, one addnsub[1..0] signal controls the top two one-level adders and another addnsub[1..0] signal controls the bottom two one-level adders. A high addnsub signal indicates addition, and a low signal indicates subtraction. The addnsub control signal can be unregistered or registered once or twice when feeding the adder blocks to match data path pipelines. The signa and signb signals serve the same function as the multiplier block signa and signb signals. The only difference is that these signals can be registered up to two times. These signals are tied to the same signa and signb signals from the multiplier and must be connected to the same clocks and control signals. Accumulator When configured for accumulation, the adder/output block output feeds back to the accumulator as shown in Figure 2-34. The accum_sload[1..0] signal synchronously loads the multiplier result to the accumulator output. This signal can be unregistered or registered once or twice. Additionally, the overflow signal indicates the accumulator has overflowed or underflowed in accumulation mode. This signal is always registered and must be externally latched in LEs if the design requires a latched overflow signal.
Summation
The output of the adder/subtractor/accumulator block feeds to an optional summation block. This block sums the outputs of the DSP block multipliers. In 9 x 9-bit mode, there are two summation blocks providing the sums of two sets of four 9 x 9-bit multipliers. In 18 x 18-bit mode, there is one summation providing the sum of one set of four 18 x 18-bit multipliers.
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Output Selection Multiplexer
The outputs from the various elements of the adder/output block are routed through an output selection multiplexer. Based on the DSP block operational mode and user settings, the multiplexer selects whether the output from the multiplier, the adder/subtractor/accumulator, or summation block feeds to the output.
Output Registers
Optional output registers for the DSP block outputs are controlled by four sets of control signals: clock[3..0], aclr[3..0], and ena[3..0]. Output registers can be used in any mode.
Modes of Operation
The adder, subtractor, and accumulate functions of a DSP block have four modes of operation:

Simple multiplier Multiply-accumulator Two-multipliers adder Four-multipliers adder Each DSP block can only support one mode. Mixed modes in the same DSP block is not supported.
1
Simple Multiplier Mode
In simple multiplier mode, the DSP block drives the multiplier sub-block result directly to the output with or without an output register. Up to four 18 x 18-bit multipliers or eight 9 x 9-bit multipliers can drive their results directly out of one DSP block. See Figure 2-35.
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Stratix Architecture
Figure 2-35. Simple Multiplier Mode
signa (1) signb (1) aclr clock ena
shiftin B
shiftin A
Data A
D ENA
Q D ENA Q D ENA Q
Data Out
CLRN
CLRN CLRN
Data B
D ENA
Q
CLRN
shiftout B
shiftout A
Note to Figure 2-35:
(1) These signals are not registered or registered once to match the data path pipeline.
DSP blocks can also implement one 36 x 36-bit multiplier in multiplier mode. DSP blocks use four 18 x 18-bit multipliers combined with dedicated adder and internal shift circuitry to achieve 36-bit multiplication. The input shift register feature is not available for the 36 x 36-bit multiplier. In 36 x 36-bit mode, the device can use the register that is normally a multiplier-result-output register as a pipeline stage for the 36 x 36-bit multiplier. Figure 2-36 shows the 36 x 36-bit multiply mode.
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Figure 2-36. 36 x 36 Multiply Mode
signa (1) signb (1) aclr clock ena
A[17..0]
D ENA
Q D Q ENA CLRN
CLRN
B[17..0]
D ENA
Q
CLRN
A[35..18]
D ENA
Q D Q ENA CLRN D Q ENA
Data Out
CLRN
36 x 36 Multiplier Adder signa (2) signb (2)
CLRN
B[35..18]
D ENA
Q
CLRN
A[35..18]
D ENA
Q D Q ENA CLRN
CLRN
B[17..0]
D ENA
Q
CLRN
A[17..0]
D ENA
Q D Q ENA CLRN
CLRN
B[35..18]
D ENA
Q
CLRN
Notes to Figure 2-36:
(1) (2) These signals are not registered or registered once to match the pipeline. These signals are not registered, registered once, or registered twice for latency to match the pipeline.
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Stratix Architecture
Multiply-Accumulator Mode
In multiply-accumulator mode (see Figure 2-37), the DSP block drives multiplied results to the adder/subtractor/accumulator block configured as an accumulator. You can implement one or two multiply-accumulators up to 18 x 18 bits in one DSP block. The first and third multiplier subblocks are unused in this mode, because only one multiplier can feed one of two accumulators. The multiply-accumulator output can be up to 52 bits--a maximum of a 36-bit result with 16 bits of accumulation. The accum_sload and overflow signals are only available in this mode. The addnsub signal can set the accumulator for decimation and the overflow signal indicates underflow condition. Figure 2-37. Multiply-Accumulate Mode
signa (1) signb (1) aclr clock ena Shiftin B Shiftin A
Data A
D ENA
Q D Q ENA CLRN D Q ENA CLRN
Data Out
Accumulator
CLRN
Data B
D ENA
Q
overflow
CLRN
Shiftout B Shiftout A
addnsub (2) signa (2) signb (2) accum_sload (2)
Notes to Figure 2-37:
(1) (2) These signals are not registered or registered once to match the data path pipeline. These signals are not registered, registered once, or registered twice for latency to match the data path pipeline.
Two-Multipliers Adder Mode
The two-multipliers adder mode uses the adder/subtractor/accumulator block to add or subtract the outputs of the multiplier block, which is useful for applications such as FFT functions and complex FIR filters. A
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single DSP block can implement two sums or differences from two 18 x 18-bit multipliers each or four sums or differences from two 9 x 9-bit multipliers each. You can use the two-multipliers adder mode for complex multiplications, which are written as: (a + jb) x (c + jd) = [(a x c) - (b x d)] + j x [(a x d) + (b x c)] The two-multipliers adder mode allows a single DSP block to calculate the real part [(a x c) - (b x d)] using one subtractor and the imaginary part [(a x d) + (b x c)] using one adder, for data widths up to 18 bits. Two complex multiplications are possible for data widths up to 9 bits using four adder/subtractor/accumulator blocks. Figure 2-38 shows an 18-bit two-multipliers adder. Figure 2-38. Two-Multipliers Adder Mode Implementing Complex Multiply
18 A 36 18 C 18 B 36 18 D 18 A 36 18 D 18 B 36 18 C Adder 37 (A x D) + (B x C) (Imaginary Part) 18 18 Subtractor 18 37 (A x C) - (B x D) (Real Part) 18 DSP Block
Four-Multipliers Adder Mode
In the four-multipliers adder mode, the DSP block adds the results of two first -stage adder/subtractor blocks. One sum of four 18 x 18-bit multipliers or two different sums of two sets of four 9 x 9-bit multipliers can be implemented in a single DSP block. The product width for each multiplier must be the same size. The four-multipliers adder mode is useful for FIR filter applications. Figure 2-39 shows the four multipliers adder mode.
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Figure 2-39. Four-Multipliers Adder Mode
signa (1) signb (1) aclr clock ena shiftin B shiftin A
Data A
D ENA
Q D ENA Q
CLRN
Adder/Subtractor
CLRN
Data B
D ENA
Q
CLRN
Data A
D ENA
Q D ENA Q D ENA Q
Data Out
CLRN
CLRN
addnsub1 (2) signa (2) signb (2) addnsub3 (2)
Summation
CLRN
Data B
D ENA
Q
CLRN
Data A
D ENA
Q D ENA Q
CLRN
Adder/Subtractor
CLRN
Data B
D ENA
Q
CLRN
Data A
D ENA
Q D ENA Q
CLRN
CLRN
Data B
D ENA
Q
CLRN
shiftout B
shiftout A
Notes to Figure 2-39:
(1) (2) These signals are not registered or registered once to match the data path pipeline. These signals are not registered, registered once, or registered twice for latency to match the data path pipeline.
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For FIR filters, the DSP block combines the four-multipliers adder mode with the shift register inputs. One set of shift inputs contains the filter data, while the other holds the coefficients loaded in serial or parallel. The input shift register eliminates the need for shift registers external to the DSP block (i.e., implemented in LEs). This architecture simplifies filter design since the DSP block implements all of the filter circuitry. One DSP block can implement an entire 18-bit FIR filter with up to four taps. For FIR filters larger than four taps, DSP blocks can be cascaded with additional adder stages implemented in LEs. Table 2-16 shows the different number of multipliers possible in each DSP block mode according to size. These modes allow the DSP blocks to implement numerous applications for DSP including FFTs, complex FIR, FIR, and 2D FIR filters, equalizers, IIR, correlators, matrix multiplication and many other functions.
Table 2-16. Multiplier Size & Configurations per DSP block DSP Block Mode
Multiplier Multiply-accumulator Two-multipliers adder Four-multipliers adder Note to Table 2-16:
(1) The number of supported multiply functions shown is based on signed/signed or unsigned/unsigned implementations.
9x9
Eight multipliers with eight product outputs Two multiply and accumulate (52 bits) Four sums of two multiplier products each Two sums of four multiplier products each
18 x 18
Four multipliers with four product outputs Two multiply and accumulate (52 bits) Two sums of two multiplier products each One sum of four multiplier products each
36 x 36 (1)
One multiplier with one product output - - -
DSP Block Interface
Stratix device DSP block outputs can cascade down within the same DSP block column. Dedicated connections between DSP blocks provide fast connections between the shift register inputs to cascade the shift register chains. You can cascade DSP blocks for 9 x 9- or 18 x 18-bit FIR filters larger than four taps, with additional adder stages implemented in LEs. If the DSP block is configured as 36 x 36 bits, the adder, subtractor, or accumulator stages are implemented in LEs. Each DSP block can route the shift register chain out of the block to cascade two full columns of DSP blocks.
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The DSP block is divided into eight block units that interface with eight LAB rows on the left and right. Each block unit can be considered half of an 18 x 18-bit multiplier sub-block with 18 inputs and 18 outputs. A local interconnect region is associated with each DSP block. Like an LAB, this interconnect region can be fed with 10 direct link interconnects from the LAB to the left or right of the DSP block in the same row. All row and column routing resources can access the DSP block's local interconnect region. The outputs also work similarly to LAB outputs as well. Nine outputs from the DSP block can drive to the left LAB through direct link interconnects and nine can drive to the right LAB though direct link interconnects. All 18 outputs can drive to all types of row and column routing. Outputs can drive right- or left-column routing. Figures 2-40 and 2-41 show the DSP block interfaces to LAB rows. Figure 2-40. DSP Block Interconnect Interface
DSP Block OA[17..0]
MultiTrack Interconnect
MultiTrack Interconnect
A1[17..0] OB[17..0]
B1[17..0] OC[17..0]
A2[17..0] OD[17..0]
B2[17..0] OE[17..0]
A3[17..0] OF[17..0]
B3[17..0] OG[17..0]
A4[17..0] OH[17..0]
B4[17..0]
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Figure 2-41. DSP Block Interface to Interconnect
C4 and C8 Interconnects Direct Link Interconnect from Adjacent LAB R4 and R8 Interconnects Nine Direct Link Outputs to Adjacent LABs Direct Link Interconnect from Adjacent LAB
18 DSP Block Row Structure 10 9 9
LAB
LAB
10
3 Control 18 [17..0] [17..0] 18
Row Interface Block DSP Block to LAB Row Interface Block Interconnect Region 18 Inputs per Row 18 Outputs per Row
A bus of 18 control signals feeds the entire DSP block. These signals include clock[0..3] clocks, aclr[0..3] asynchronous clears, ena[1..4] clock enables, signa, signb signed/unsigned control signals, addnsub1 and addnsub3 addition and subtraction control signals, and accum_sload[0..1] accumulator synchronous loads. The
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clock signals are routed from LAB row clocks and are generated from specific LAB rows at the DSP block interface. The LAB row source for control signals, data inputs, and outputs is shown in Table 2-17.
Table 2-17. DSP Block Signal Sources & Destinations LAB Row at Interface
1 2 3
Control Signals Generated
signa aclr0 accum_sload0 addnsub1 clock0 ena0 aclr1 clock1 ena1 aclr2 clock2 ena2 sign_b clock3 ena3 clear3 accum_sload1 addnsub3
Data Inputs
A1[17..0] B1[17..0] A2[17..0]
Data Outputs
OA[17..0] OB[17..0] OC[17..0]
4
B2[17..0]
OD[17..0]
5
A3[17..0]
OE[17..0]
6
B3[17..0]
OF[17..0]
7 8
A4[17..0] B4[17..0]
OG[17..0] OH[17..0]
PLLs & Clock Networks
Stratix devices provide a hierarchical clock structure and multiple PLLs with advanced features. The large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast PLLs provides a complete clock management solution.
Global & Hierarchical Clocking
Stratix devices provide 16 dedicated global clock networks, 16 regional clock networks (four per device quadrant), and 8 dedicated fast regional clock networks (for EP1S10, EP1S20, and EP1S25 devices), and 16 dedicated fast regional clock networks (for EP1S30 EP1S40, and EP1S60, and EP1S80 devices). These clocks are organized into a hierarchical clock structure that allows for up to 22 clocks per device region with low skew and delay. This hierarchical clocking scheme provides up to 48 unique clock domains within Stratix devices.
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There are 16 dedicated clock pins (CLK[15..0]) to drive either the global or regional clock networks. Four clock pins drive each side of the device, as shown in Figure 2-42. Enhanced and fast PLL outputs can also drive the global and regional clock networks.
Global Clock Network
These clocks drive throughout the entire device, feeding all device quadrants. The global clock networks can be used as clock sources for all resources within the device--IOEs, LEs, DSP blocks, and all memory blocks. These resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin. The global clock networks can also be driven by internal logic for internally generated global clocks and asynchronous clears, clock enables, or other control signals with large fanout. Figure 2-42 shows the 16 dedicated CLK pins driving global clock networks.
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Figure 2-42. Global Clocking Note (1)
CLK[15..12]
Global Clock [15..0]
CLK[3..0]
Global Clock [15..0]
CLK[11..8]
CLK[7..4]
Note to Figure 2-42:
(1) The corner fast PLLs can also be driven through the global or regional clock networks. The global or regional clock input to the fast PLL can be driven by an output from another PLL, a pin-driven global or regional clock, or internallygenerated global signals.
Regional Clock Network
There are four regional clock networks within each quadrant of the Stratix device that are driven by the same dedicated CLK[15..0] input pins or from PLL outputs. From a top view of the silicon, RCLK[0..3] are in the top left quadrant, RCLK[8..11] are in the top-right quadrant, RCLK[4..7] are in the bottom-left quadrant, and RCLK[12..15] are in the bottom-right quadrant. The regional clock networks only pertain to the quadrant they drive into. The regional clock networks provide the lowest clock delay and skew for logic contained within a single quadrant. RCLK cannot be driven by internal logic. The CLK clock pins symmetrically drive the RCLK networks within a particular quadrant, as shown in Figure 2-43. See Figures 2-50 and 2-51 for RCLK connections from PLLs and CLK pins.
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Figure 2-43. Regional Clocks
RCLK[2..3] RCLK[11..10]
CLK[15..12]
RCLK[1..0] CLK[3..0]
RCLK[9..8] CLK[11..8]
RCLK[4..5]
RCLK[14..15]
CLK[7..4] Regional Clocks Only Drive a Device Quadrant from Specified CLK Pins or PLLs within that Quadrant RCLK[6..7] RCLK[12..13]
Fast Regional Clock Network
In EP1S25, EP1S20, and EP1S10 devices, there are two fast regional clock networks, FCLK[1..0], within each quadrant, fed by input pins that can connect to fast regional clock networks (see Figure 2-44). In EP1S30 and larger devices, there are two fast regional clock networks within each half-quadrant (see Figure 2-45). Dual-purpose FCLK pins drive the fast clock networks. All devices have eight FCLK pins to drive fast regional clock networks. Any I/O pin can drive a clock or control signal onto any fast regional clock network with the addition of a delay. This signal is driven via the I/O interconnect. The fast regional clock networks can also be driven from internal logic elements.
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Figure 2-44. EP1S25, EP1S20 & EP1S10 Device Fast Clock Pin Connections to Fast Regional Clocks
FCLK[1..0] FCLK[7..6]
2 (1), (2) 2 (1), (2)
2
2
FCLK[1..0]
FCLK[1..0]
FCLK[1..0]
FCLK[1..0]
2 (1), (2) 2 (1), (2)
2
2
FCLK[3..2]
FCLK[5..4]
Notes to Figure 2-44:
(1) (2) This is a set of two multiplexers. In addition to the FCLK pin inputs, there is also an input from the I/O interconnect.
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Figure 2-45. EP1S30 Device Fast Regional Clock Pin Connections to Fast Regional Clocks
FCLK1 FCLK0 FCLK7 FCLK6
(1), (2)
(1), (2) (1), (2) (1), (2)
fclk[1..0]
(1), (2)
(1), (2) (1), (2) (1), (2)
FCLK3
FCLK2
FCLK5
FCLK4
Notes to Figure 2-45:
(1) (2) This is a set of two multiplexers. In addition to the FCLK pin inputs, there is also an input from the I/O interconnect.
Combined Resources
Within each region, there are 22 distinct dedicated clocking resources consisting of 16 global clock lines, four regional clock lines, and two fast regional clock lines. Multiplexers are used with these clocks to form eight bit busses to drive LAB row clocks, column IOE clocks, or row IOE clocks. Another multiplexer is used at the LAB level to select two of the eight row clocks to feed the LE registers within the LAB. See Figure 2-46.
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Figure 2-46. Regional Clock Bus
Clocks Available to a Quadrant or Half-Quadrant Global Clock Network [15..0] Regional Clock Network [3..0] Fast Regional Clock Network [1..0] Horizontal I/O Cell IO_CLK[7..0] Clock [21..0] Lab Row Clock [7..0] Vertical I/O Cell IO_CLK[7..0]
IOE clocks have horizontal and vertical block regions that are clocked by eight I/O clock signals chosen from the 22 quadrant or half-quadrant clock resources. Figures 2-47 and 2-48 show the quadrant and halfquadrant relationship to the I/O clock regions, respectively. The vertical regions (column pins) have less clock delay than the horizontal regions (row pins).
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Figure 2-47. EP1S10, EP1S20 & EP1S25 Device I/O Clock Groups
IO_CLKA[7..0] IO_CLKB[7..0]
8
8
I/O Clock Regions
8
22 Clocks in the Quadrant
22 Clocks in the Quadrant
IO_CLKH[7..0]
8
IO_CLKC[7..0]
8
IO_CLKG[7..0]
22 Clocks in the Quadrant 22 Clocks in the Quadrant
IO_CLKD[7..0]
8
8
8
IO_CLKF[7..0]
IO_CLKE[7..0]
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Figure 2-48. EP1S30, EP1S40, EP1S60, EP1S80 Device I/O Clock Groups
IO_CLKA[7:0] IO_CLKB[7:0] IO_CLKC[7:0] IO_CLKD[7:0]
8
8
8
8 I/O Clock Regions
8
8
IO_CLKP[7:0] 22 Clocks in the Half-Quadrant 8 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 8
IO_CLKE[7:0]
IO_CLKO[7:0]
IO_CLKF[7:0]
8
8
IO_CLKN[7:0] 22 Clocks in the Half-Quadrant 8 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 22 Clocks in the Half-Quadrant 8
IO_CLKG[7:0]
IO_CLKM[7:0]
IO_CLKH[7:0]
8
8
8
8
IO_CLKL[7:0]
IO_CLKK[7:0]
IO_CLKJ[7:0]
IO_CLKI[7:0]
You can use the Quartus II software to control whether a clock input pin is either global, regional, or fast regional. The Quartus II software automatically selects the clocking resources if not specified.
Enhanced & Fast PLLs
Stratix devices provide robust clock management and synthesis using up to four enhanced PLLs and eight fast PLLs. These PLLs increase performance and provide advanced clock interfacing and clockfrequency synthesis. With features such as clock switchover, spread spectrum clocking, programmable bandwidth, phase and delay control, and PLL reconfiguration, the Stratix device's enhanced PLLs provide you with complete control of your clocks and system timing. The fast PLLs
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provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for high-speed differential I/O support. Enhanced and fast PLLs work together with the Stratix high-speed I/O and advanced clock architecture to provide significant improvements in system performance and bandwidth. The Quartus II software enables the PLLs and their features without requiring any external devices. Table 2-18 shows the PLLs available for each Stratix device.
Table 2-18. Stratix Device PLL Availability Fast PLLs Device 1
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
Enhanced PLLs 8 9 10 5(1) v v v 6(1) v v v v v v v v(3) v(3) v v v v 11(2) 12(2)
2 v v v v v v v
3 v v v v v v v
4 v v v v v v v
7
v v v v v v v
v (3) v (3)
v (3) v (3)
v (3) v (3)
v (3) v (3)
v v v v
v v
v v
v v
v v
Notes to Table 2-18:
(1) (2) (3) PLLs 5 and 6 each have eight single-ended outputs or four differential outputs. PLLs 11 and 12 each have one single-ended output. EP1S30 and EP1S40 devices do not support these PLLs in the 780-pin FineLine BGA(R) package.
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Table 2-19 shows the enhanced PLL and fast PLL features in Stratix devices.
Table 2-19. Stratix PLL Features Feature
Clock multiplication and division Phase shift Delay shift Clock switchover PLL reconfiguration Programmable bandwidth Spread spectrum clocking Programmable duty cycle Number of internal clock outputs Number of external clock outputs Number of feedback clock inputs Notes to Table 2-19:
(1) (2) (3) (4) (5) (6) For enhanced PLLs, m, n, range from 1 to 512 and post-scale counters g, l, e range from 1 to 1024 with 50% duty cycle. With a non-50% duty cycle the post-scale counters g, l, e range from 1 to 512. For fast PLLs, m and post-scale counters range from 1 to 32. The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by 8. For degree increments, Stratix devices can shift all output frequencies in increments of at least 45 . Smaller degree increments are possible depending on the frequency and divide parameters. PLLs 7, 8, 9, and 10 have two output ports per PLL. PLLs 1, 2, 3, and 4 have three output ports per PLL. Every Stratix device has two enhanced PLLs (PLLs 5 and 6) with either eight single-ended outputs or four differential outputs each. Two additional enhanced PLLs (PLLs 11 and 12) in EP1S80, EP1S60, and EP1S40 devices each have one single-ended output. Devices in the 780 pin FineLine BGA packages do not support PLLs 11 and 12. Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data channel to generate txclkout. Every Stratix device has two enhanced PLLs with one single-ended or differential external feedback input per PLL.
Enhanced PLL
m/(n x post-scale counter) (1) Down to 156.25-ps increments (3), (4) 250-ps increments for 3 ns
Fast PLL
m/(post-scale counter) (2) Down to 125-ps increments (3), (4)
v v v v v
6 Four differential/eight singled-ended or one single-ended (6) 2 (8)
v
3 (5) (7)
(7) (8)
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Figure 2-49 shows a top-level diagram of the Stratix device and PLL floorplan. Figure 2-49. PLL Locations
CLK[15..12] 5 11
FPLL7CLK
7
10
FPLL10CLK
CLK[3..0]
1 2
4 3
CLK[8..11]
PLLs
FPLL8CLK
8
9
FPLL9CLK
6
12
CLK[7..4]
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Figure 2-50 shows the global and regional clocking from the PLL outputs and the CLK pins. Figure 2-50. Global & Regional Clock Connections from Side Pins & Fast PLL Outputs Note (1), (2)
RCLK1 RCLK0
FPLL7CLK l0 PLL 7 l1 g0
G1 G0 G2
G3 G9
G8
G10 G11
RCLK9 RCLK8
l0 l1 PLL 10 g0 FPLL10CLK
CLK0 CLK1
l0 PLL 1 l1 g0
l0 l1 PLL 4 g0
CLK10 CLK11
CLK2 CLK3
l0 2 PLL 2 l1 g0
l0 2 l1 PLL 3 g0
CLK8 CLK9
l0 PLL 8 l1 g0
l0 l1 PLL 9 g0
FPLL8CLK
FPLL9CLK
RCLK4 RCLK5
Regional Clocks Global Clocks
RCLK14 RCLK15
Regional Clocks
Notes to Figure 2-50:
(1) (2) PLLs 1 to 4 and 7 to 10 are fast PLLs. PLLs 5, 6, 11, and 12 are enhanced PLLs. The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. A pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL.
Figure 2-51 shows the global and regional clocking from enhanced PLL outputs and top CLK pins.
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Figure 2-51. Global & Regional Clock Connections from Top Clock Pins & Enhanced PLL Outputs Note (1)
PLL5_OUT[3..0] CLK14 (1) PLL5_FB CLK15 (2) CLK12 (1) CLK13 (2)
E[0..3] PLL 5 PLL 11
L0 L1 G0 G1 G2 G3
G0 G1 G2 G3 L0 L1
PLL11_OUT RCLK10 RCLK11
Regional Clocks
RCLK2 RCLK3 G12 G13 G14 G15
Global Clocks
G4 G5 G6 G7
Regional Clocks
RCLK6 RCLK7 RCLK12 RCLK13
PLL12_OUT
L0 L1 G0 G1 G2 G3 PLL 6
G0 G1 G2 G3 L0 L1 PLL 12
PLL6_OUT[3..0]
PLL6_FB CLK4 (1) CLK5 (2)
CLK6 (1)
CLK7 (2)
Notes to Figure 2-51:
(1) (2) (3) (4) PLLs 1 to 4 and 7 to 10 are fast PLLs. PLLs 5, 6, 11, and 12 are enhanced PLLs. CLK4, CLK6, CLK12, and CLK14 feed the corresponding PLL's inclk0 port. CLK5, CLK7, CLK13, and CLK15 feed the corresponding PLL's inclk1 port. The EP1S40 device in the 780-pin FineLine BGA package does not support PLLs 11 and 12.
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Enhanced PLLs
Stratix devices contain up to four enhanced PLLs with advanced clock management features. Figure 2-52 shows a diagram of the enhanced PLL. Figure 2-52. Stratix Enhanced PLL
Post-Scale Counters VCO Phase Selection Selectable at Each PLL Output Port From Adjacent PLL t Regional Clocks Clock Switch-Over Circuitry INCLK0 /n t PFD Charge Pump Loop Filter 8 VCO /g0 /l1 Phase Frequency Detector Spread Spectrum 4 t Programmable Time Delay on Each PLL Port
/l0
t
Global Clocks
INCLK1
/g1
t t t I/O buffers (2) To I/O buffers or general routing
(1)
t
/m
/g2
/g3 FBIN Lock Detect & Filter VCO Phase Selection Affecting All Outputs /e0
t t t t I/O Buffers (3)
/e1
4
/e2 /e3
Notes to Figure 2-52:
(1) (2) (3) (4) External feedback is available in PLLs 5 and 6. This single-ended external output is available from the g0 counter for PLLs 11 and 12. These four counters and external outputs are available in PLLs 5 and 6. This connection is only available on EP1S40 and larger Stratix devices. For example, PLLs 5 and 11 are adjacent and PLLs 6 and 12 are adjacent. The EP1S40 device in the 780-pin FineLine BGA package does not support PLLs 11 and 12.
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Clock Multiplication & Division
Each Stratix device enhanced PLL provides clock synthesis for PLL output ports using m/(n x post-scale counter) scaling factors. The input clock is divided by a pre-scale divider, n, and is then multiplied by the m feedback factor. The control loop drives the VCO to match fIN x (m/n). Each output port has a unique post-scale counter that divides down the high-frequency VCO. For multiple PLL outputs with different frequencies, the VCO is set to the least common multiple of the output frequencies that meets its frequency specifications. Then, the post-scale dividers scale down the output frequency for each output port. For example, if output frequencies required from one PLL are 33 and 66 MHz, set the VCO to 330 MHz (the least common multiple in the VCO's range). There is one pre-scale counter, n, and one multiply counter, m, per PLL, with a range of 1 to 512 on each. There are two post-scale counters (l) for regional clock output ports, four counters (g) for global clock output ports, and up to four counters (e) for external clock outputs, all ranging from 1 to 1024 with a 50% duty cycle setting. The post-scale counters range from 1 to 512 with any non-50% duty cycle setting. The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered.
Clock Switchover
To effectively develop high-reliability network systems, clocking schemes must support multiple clocks to provide redundancy. For this reason, Stratix device enhanced PLLs support a flexible clock switchover capability. Figure 2-53 shows a block diagram of the switchover circuit.The switchover circuit is configurable, so you can define how to implement it. Clock-sense circuitry automatically switches from the primary to secondary clock for PLL reference when the primary clock signal is not present.
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Figure 2-53. Clock Switchover Circuitry
CLK0_BAD CLK1_BAD Active Clock SMCLKSW
Clock Sense
Switch-Over State Machine
CLKLOSS
CLKSWITCH
t INCLK0 INCLK1 MUXOUT
n Counter
PFD
FBCLK
Enhanced PLL
There are two possible ways to use the clock switchover feature.
Use automatic switchover circuitry for switching between inputs of the same frequency. For example, in applications that require a redundant clock with the same frequency as the primary clock, the switchover state machine generates a signal that controls the multiplexer select input on the bottom of Figure 2-53. In this case, the secondary clock becomes the reference clock for the PLL. Use the clkswitch input for user- or system-controlled switch conditions. This is possible for same-frequency switchover or to switch between inputs of different frequencies. For example, if inclk0 is 66 MHz and inclk1 is 100 MHz, you must control the switchover because the automatic clock-sense circuitry cannot monitor primary and secondary clock frequencies with a frequency difference of more than 20%. This feature is useful when clock sources can originate from multiple cards on the backplane, requiring a system-controlled switchover between frequencies of operation. You can use clkswitch together with the lock signal to trigger the switch from a clock that is running but becomes unstable and cannot be locked onto.
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During switchover, the PLL VCO continues to run and will either slow down or speed up, generating frequency drift on the PLL outputs. The clock switchover transitions without any glitches. After the switch, there is a finite resynchronization period to lock onto new clock as the VCO ramps up. The exact amount of time it takes for the PLL to relock relates to the PLL configuration and may be adjusted by using the programmable bandwidth feature of the PLL. The specification for the maximum time to relock is 100 s.
f
For more information on clock switchover, see AN 313, Implementing Clock Switchover in Stratix & Stratix GX Devices.
PLL Reconfiguration
The PLL reconfiguration feature enables system logic to change Stratix device enhanced PLL counters and delay elements without reloading a Programmer Object File (.pof). This provides considerable flexibility for frequency synthesis, allowing real-time PLL frequency and output clock delay variation. You can sweep the PLL output frequencies and clock delay in prototype environments. The PLL reconfiguration feature can also dynamically or intelligently control system clock speeds or tCO delays in end systems. Clock delay elements at each PLL output port implement variable delay. Figure 2-54 shows a diagram of the overall dynamic PLL control feature for the counters and the clock delay elements. The configuration time is less than 20 s for the enhanced PLL using a input shift clock rate of 22 MHz. The charge pump, loop filter components, and phase shifting using VCO phase taps cannot be dynamically adjusted.
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Figure 2-54. Dynamically Programmable Counters & Delays in Stratix Device Enhanced PLLs
Counters and Clock Delay Settings are Programmable All Output Counters and Clock Delay Settings can be Programmed Dynamically
fREF scandata scanclk
/n
t
PFD
Charge Pump
Loop Filter
VCO
/g
t
/m
t
scanaclr
/l
t
/e
t
PLL reconfiguration data is shifted into serial registers from the logic array or external devices. The PLL input shift data uses a reference input shift clock. Once the last bit of the serial chain is clocked in, the register chain is synchronously loaded into the PLL configuration bits. The shift circuitry also provides an asynchronous clear for the serial registers.
f
For more information on PLL reconfiguration, see AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices.
Programmable Bandwidth
You have advanced control of the PLL bandwidth using the programmable control of the PLL loop characteristics, including loop filter and charge pump. The PLL's bandwidth is a measure of its ability to track the input clock and jitter. A high-bandwidth PLL can quickly lock onto a reference clock and react to any changes in the clock. It also will allow a wide band of input jitter spectrum to pass to the output. A lowbandwidth PLL will take longer to lock, but it will attenuate all highfrequency jitter components. The Quartus II software can adjust PLL characteristics to achieve the desired bandwidth. The programmable
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bandwidth is tuned by varying the charge pump current, loop filter resistor value, high frequency capacitor value, and m counter value. You can manually adjust these values if desired. Bandwidth is programmable from 200 kHz to 1.5 MHz.
External Clock Outputs
Enhanced PLLs 5 and 6 each support up to eight single-ended clock outputs (or four differential pairs). Differential SSTL and HSTL outputs are implemented using 2 single-ended output buffers which are programmed to have opposite polarity. In Quartus II software, simply assign the appropriate differential I/O standard and the software will implement the inversion. See Figure 2-55.
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Figure 2-55. External Clock Outputs for PLLs 5 & 6
From IOE (1), (2) pll_out0p (3), (4) (3) e0 Counter
From IOE (1) From IOE (1)
pll_out0n (3), (4)
pll_out1p (3), (4)
e1 Counter
4
From IOE (1)
pll_out1n (3), (4)
From IOE (1)
pll_out2p (3), (4)
e2 Counter
pll_out2n (3), (4) From IOE (1) From IOE (1)
pll_out3p (3), (4)
e3 Counter
From IOE (1)
pll_out3n (3), (4)
Notes to Figure 2-55:
(1) (2) (3) (4) The design can use each external clock output pin as a general-purpose output pin from the logic array. These pins are multiplexed with IOE outputs. Two single-ended outputs are possible per output counter either two outputs of the same frequency and phase or one shifted 180 . EP1S10, EP1S20, and EP1S25 devices in 672-pin BGA and 484- and 672-pin FineLine BGA packages only have two pairs of external clocks (i.e., pll_out0p, pll_out0n, pll_out1p, and pll_out1n). Differential SSTL and HSTL outputs are implemented using two single-ended output buffers, which are programmed to have opposite polarity.
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Any of the four external output counters can drive the single-ended or differential clock outputs for PLLs 5 and 6. This means one counter or frequency can drive all output pins available from PLL 5 or PLL 6. Each pair of output pins (four pins total) has dedicated VCC and GND pins to reduce the output clock's overall jitter by providing improved isolation from switching I/O pins. For PLLs 5 and 6, each pin of a single-ended output pair can either be in phase or 180 out of phase. The clock output pin pairs support the same I/O standards as standard output pins (in the top and bottom banks) as well as LVDS, LVPECL, 3.3-V PCML, HyperTransport technology, differential HSTL, and differential SSTL. Table 2-20 shows which I/O standards the enhanced PLL clock pins support. When in single-ended or differential mode, the two outputs operate off the same power supply. Both outputs use the same standards in single-ended mode to maintain performance. You can also use the external clock output pins as user output pins if external enhanced PLL clocking is not needed.
Table 2-20. I/O Standards Supported for Enhanced PLL Pins (Part 1 of 2) Input I/O Standard INCLK
LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X 1.0 LVPECL 3.3-V PCML LVDS HyperTransport technology Differential HSTL Differential SSTL 3.3-V GTL 3.3-V GTL+ 1.5-V HSTL Class I
Output PLLENABLE v v EXTCLK v v v v v v v v v v v v v
FBIN v v v v v v v v v v v
v v v v v v v v v v v v v v v
v v v
v v v
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Table 2-20. I/O Standards Supported for Enhanced PLL Pins (Part 2 of 2) Input I/O Standard INCLK
1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II SSTL-18 Class I SSTL-18 Class II SSTL-2 Class I SSTL-2 Class II SSTL-3 Class I SSTL-3 Class II AGP (1x and 2x ) CTT
Output PLLENABLE EXTCLK v v v v v v v v v v v
FBIN v v v v v v v v v v v
v v v v v v v v v v v
Enhanced PLLs 11 and 12 support one single-ended output each (see Figure 2-56). These outputs do not have their own VCC and GND signals. Therefore, to minimize jitter, do not place switching I/O pins next to this output pin. Figure 2-56. External Clock Outputs for Enhanced PLLs 11 & 12
g0 Counter
CLK13n, I/O, PLL11_OUT or CLK6n, I/O, PLL12_OUT (1)
From Internal Logic or IOE
Note to Figure 2-56:
(1) For PLL 11, this pin is CLK13n; for PLL 12 this pin is CLK7n.
Stratix devices can drive any enhanced PLL driven through the global clock or regional clock network to any general I/O pin as an external output clock. The jitter on the output clock is not guaranteed for these cases.
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Clock Feedback
The following four feedback modes in Stratix device enhanced PLLs allow multiplication and/or phase and delay shifting:
Zero delay buffer: The external clock output pin is phase-aligned with the clock input pin for zero delay. Altera recommends using the same I/O standard on the input clock and the output clocks for optimum performance. External feedback: The external feedback input pin, FBIN, is phasealigned with the clock input, CLK, pin. Aligning these clocks allows you to remove clock delay and skew between devices. This mode is only possible for PLLs 5 and 6. PLLs 5 and 6 each support feedback for one of the dedicated external outputs, either one single-ended or one differential pair. In this mode, one e counter feeds back to the PLL FBIN input, becoming part of the feedback loop. Altera recommends using the same I/O standard on the input clock, the FBIN pin, and the output clocks for optimum performance. Normal mode: If an internal clock is used in this mode, it is phasealigned to the input clock pin. The external clock output pin will have a phase delay relative to the clock input pin if connected in this mode. You define which internal clock output from the PLL should be phase-aligned to the internal clock pin. No compensation: In this mode, the PLL will not compensate for any clock networks or external clock outputs.
Phase & Delay Shifting
Stratix device enhanced PLLs provide advanced programmable phase and clock delay shifting. These parameters are set in the Quartus II software. Phase Delay The Quartus II software automatically sets the phase taps and counter settings according to the phase shift entry. You enter a desired phase shift and the Quartus II software automatically sets the closest setting achievable. This type of phase shift is not reconfigurable during system operation. For phase shifting, enter a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. You can select phase-shifting values in time units with a resolution of 156.25 to 416.66 ps. This resolution is a function of frequency input and the multiplication and division factors (that is, it is a function of the VCO period), with the finest step being equal to an eighth (x0.125) of the VCO period. Each clock output counter can choose a different phase of the
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VCO period from up to eight taps for individual fine step selection. Also, each clock output counter can use a unique initial count setting to achieve individual coarse shift selection in steps of one VCO period. The combination of coarse and fine shifts allows phase shifting for the entire input clock period. The equation to determine the precision of the phase shifting in degrees is: 45 / post-scale counter value. Therefore, the maximum step size is 45 , and smaller steps are possible depending on the multiplication and division ratio necessary on the output counter port. This type of phase shift provides the highest precision since it is the least sensitive to process, supply, and temperature variation. Clock Delay In addition to the phase shift feature, the ability to fine tune the t clock delay provides advanced time delay shift control on each of the four PLL outputs. There are time delays for each post-scale counter (e, g, or l) from the PLL, the n counter, and m counter. Each of these can shift in 250-ps increments for a range of 3.0 ns. The m delay shifts all outputs earlier in time, while n delay shifts all outputs later in time. Individual delays on post-scale counters (e, g, and l) provide positive delay for each output. Table 2-21 shows the combined delay for each output for normal or zero delay buffer mode where te, tg, or tl is unique for each PLL output. The tOUTPUT for a single output can range from -3 ns to +6 ns. The total delay shift difference between any two PLL outputs, however, must be less than 3 ns. For example, shifts on two outputs of -1 and +2 ns is allowed, but not -1 and +2.5 ns because these shifts would result in a difference of 3.5 ns. If the design uses external feedback, the te delay will remove delay from outputs, represented by a negative sign (see Table 2-21). This effect occurs because the te delay is then part of the feedback loop.
Table 2-21. Output Clock Delay for Enhanced PLLs Normal or Zero Delay Buffer Mode
teOUTPUT = tn -tm + te tgOUTPUT = tn -tm + tg tlOUTPUT = tn -tm + tl Note to Table 2-21:
(1)
External Feedback Mode
teOUTPUT = tn -tm -te (1) tgOUTPUT = tn -tm + tg tlOUTPUT = tn -tm + tl
te removes delay from outputs in external feedback mode.
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The variation due to process, voltage, and temperature is about 15% on the delay settings. PLL reconfiguration can control the clock delay shift elements, but not the VCO phase shift multiplexers, during system operation.
Spread-Spectrum Clocking
Stratix device enhanced PLLs use spread-spectrum technology to reduce electromagnetic interference generation from a system by distributing the energy over a broader frequency range. The enhanced PLL typically provides 0.5% down spread modulation using a triangular profile. The modulation frequency is programmable. Enabling spread-spectrum for a PLL affects all of its outputs.
Lock Detect
The lock output indicates that there is a stable clock output signal in phase with the reference clock. Without any additional circuitry, the lock signal may toggle as the PLL begins tracking the reference clock. You may need to gate the lock signal for use as a system control. The lock signal from the locked port can drive the logic array or an output pin. Whenever the PLL loses lock (for example, inclk jitter, clock switchover, PLL reconfiguration, power supply noise, and so on), the PLL must be reset with the areset signal to guarantee correct phase relationship between the PLL output clocks. If the phase relationship between the input clock versus output clock, and between different output clocks from the PLL is not important in the design, then the PLL need not be reset.
f
See the Stratix FPGA Errata Sheet for more information on implementing the gated lock signal in a design.
Programmable Duty Cycle
The programmable duty cycle allows enhanced PLLs to generate clock outputs with a variable duty cycle. This feature is supported on each enhanced PLL post-scale counter (g0..g3, l0..l3, e0..e3). The duty cycle setting is achieved by a low and high time count setting for the post-scale dividers. The Quartus II software uses the frequency input and the required multiply or divide rate to determine the duty cycle choices.
Advanced Clear & Enable Control
There are several control signals for clearing and enabling PLLs and their outputs. You can use these signals to control PLL resynchronization and gate PLL output clocks for low-power applications.
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The pllenable pin is a dedicated pin that enables/disables PLLs. When the pllenable pin is low, the clock output ports are driven by GND and all the PLLs go out of lock. When the pllenable pin goes high again, the PLLs relock and resynchronize to the input clocks. You can choose which PLLs are controlled by the pllenable signal by connecting the pllenable input port of the altpll megafunction to the common pllenable input pin. The areset signals are reset/resynchronization inputs for each PLL. The areset signal should be asserted every time the PLL loses lock to guarantee correct phase relationship between the PLL output clocks. Users should include the areset signal in designs if any of the following conditions are true:

PLL Reconfiguration or Clock switchover enables in the design. Phase relationships between output clocks need to be maintained after a loss of lock condition
The device input pins or logic elements (LEs) can drive these input signals. When driven high, the PLL counters will reset, clearing the PLL output and placing the PLL out of lock. The VCO will set back to its nominal setting (~700 MHz). When driven low again, the PLL will resynchronize to its input as it relocks. If the target VCO frequency is below this nominal frequency, then the output frequency will start at a higher value than desired as the PLL locks. If the system cannot tolerate this, the clkena signal can disable the output clocks until the PLL locks. The pfdena signals control the phase frequency detector (PFD) output with a programmable gate. If you disable the PFD, the VCO operates at its last set value of control voltage and frequency with some long-term drift to a lower frequency. The system continues running when the PLL goes out of lock or the input clock is disabled. By maintaining the last locked frequency, the system has time to store its current settings before shutting down. You can either use your own control signal or a clkloss status signal to trigger pfdena. The clkena signals control the enhanced PLL regional and global outputs. Each regional and global output port has its own clkena signal. The clkena signals synchronously disable or enable the clock at the PLL output port by gating the outputs of the g and l counters. The clkena signals are registered on the falling edge of the counter output clock to enable or disable the clock without glitches. Figure 2-57 shows the waveform example for a PLL clock port enable. The PLL can remain locked independent of the clkena signals since the loop-related counters are not affected. This feature is useful for applications that require a low power or sleep mode. Upon re-enabling, the PLL does not need a
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resynchronization or relock period. The clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during resynchronization. The extclkena signals work in the same way as the clkena signals, but they control the external clock output counters (e0, e1, e2, and e3). Upon re-enabling, the PLL does not need a resynchronization or relock period unless the PLL is using external feedback mode. In order to lock in external feedback mode, the external output must drive the board trace back to the FBIN pin. Figure 2-57. extclkena Signals
COUNTER OUTPUT
CLKENA
CLKOUT
Fast PLLs
Stratix devices contain up to eight fast PLLs with high-speed serial interfacing ability, along with general-purpose features. Figure 2-58 shows a diagram of the fast PLL.
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Figure 2-58. Stratix Device Fast PLL
Post-Scale Counters diffioclk1 (2) Global or regional clock txload_en (3)
/l0 VCO Phase Selection Selectable at each PLL Output Port Phase Frequency Detector /l1
rxload_en (3) Global or regional clock diffioclk2 (2)
Global or regional clock (1)
Clock Input
PFD
Charge Pump
Loop Filter
8 VCO
/g0
Global or regional clock
/m
Notes to Figure 2-58:
(1) (2) (3) The global or regional clock input can be driven by an output from another PLL or any dedicated CLK or FCLK pin. It cannot be driven by internally-generated global signals. In high-speed differential I/O support mode, this high-speed PLL clock feeds the SERDES. Stratix devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode. This signal is a high-speed differential I/O support SERDES control signal.
Clock Multiplication & Division
Stratix device fast PLLs provide clock synthesis for PLL output ports using m/(post scaler) scaling factors. The input clock is multiplied by the m feedback factor. Each output port has a unique post scale counter to divide down the high-frequency VCO. There is one multiply divider, m, per fast PLL with a range of 1 to 32. There are two post scale L dividers for regional and/or LVDS interface clocks, and g0 counter for global clock output port; all range from 1 to 32. In the case of a high-speed differential interface, set the output counter to 1 to allow the high-speed VCO frequency to drive the SERDES. When used for clocking the SERDES, the m counter can range from 1 to 30. The VCO frequency is equal to fINxm, where VCO frequency must be between 300 and 1000 MHz.
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External Clock Inputs
Each fast PLL supports single-ended or differential inputs for source synchronous transmitters or for general-purpose use. Sourcesynchronous receivers support differential clock inputs. The fast PLL inputs are fed by CLK[0..3], CLK[8..11], and FPLL[7..10]CLK pins, as shown in Figure 2-50 on page 2-85. Table 2-22 shows the I/O standards supported by fast PLL input pins.
Table 2-22. Fast PLL Port I/O Standards (Part 1 of 2) Input I/O Standard INCLK
LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X 1.0 LVPECL 3.3-V PCML LVDS HyperTransport technology Differential HSTL Differential SSTL 3.3-V GTL 3.3-V GTL+ 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II SSTL-18 Class I SSTL-18 Class II SSTL-2 Class I
PLLENABLE v v
v v v v v
v v v v v
v v v v v
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Table 2-22. Fast PLL Port I/O Standards (Part 2 of 2) Input I/O Standard INCLK
SSTL-2 Class II SSTL-3 Class I SSTL-3 Class II AGP (1x and 2x ) CTT
PLLENABLE
v v v v
Table 2-23 shows the performance on each of the fast PLL clock inputs when using LVDS, LVPECL, 3.3-V PCML, or HyperTransport technology.
Table 2-23. LVDS Performance on Fast PLL Input Fast PLL Clock Input
CLK0, CLK2, CLK9, CLK11, FPLL7CLK, FPLL8CLK, FPLL9CLK, FPLL10CLK CLK1, CLK3, CLK8, CLK10 Note to Table 2-23:
(1) See the chapter DC & Switching Characteristics of the Stratix Device Handbook, Volume 1 for more information.
Maximum Input Frequency (MHz)
717(1)
645
External Clock Outputs
Each fast PLL supports differential or single-ended outputs for sourcesynchronous transmitters or for general-purpose external clocks. There are no dedicated external clock output pins. Any I/O pin can be driven by the fast PLL global or regional outputs as an external output pin. The I/O standards supported by any particular bank determines what standards are possible for an external clock output driven by the fast PLL in that bank.
Phase Shifting
Stratix device fast PLLs have advanced clock shift capability that enables programmable phase shifts. You can enter a phase shift (in degrees or time units) for each PLL clock output port or for all outputs together in one shift. You can perform phase shifting in time units with a resolution range of 125 to 416.66 ps. This resolution is a function of the VCO period, with the finest step being equal to an eighth (x0.125) of the VCO period.
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Control Signals
The fast PLL has the same lock output, pllenable input, and areset input control signals as the enhanced PLL. If the input clock stops and causes the PLL to lose lock, then the PLL must be reset for correct phase shift operation. For more information on high-speed differential I/O support, see "HighSpeed Differential I/O Support" on page 2-130.
I/O Structure
IOEs provide many features, including:

Dedicated differential and single-ended I/O buffers 3.3-V, 64-bit, 66-MHz PCI compliance 3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance Joint Test Action Group (JTAG) boundary-scan test (BST) support Differential on-chip termination for LVDS I/O standard Programmable pull-up during configuration Output drive strength control Slew-rate control Tri-state buffers Bus-hold circuitry Programmable pull-up resistors Programmable input and output delays Open-drain outputs DQ and DQS I/O pins Double-data rate (DDR) Registers
The IOE in Stratix devices contains a bidirectional I/O buffer, six registers, and a latch for a complete embedded bidirectional single data rate or DDR transfer. Figure 2-59 shows the Stratix IOE structure. The IOE contains two input registers (plus a latch), two output registers, and two output enable registers. The design can use both input registers and the latch to capture DDR input and both output registers to drive DDR outputs. Additionally, the design can use the output enable (OE) register for fast clock-to-output enable timing. The negative edge-clocked OE register is used for DDR SDRAM interfacing. The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins.
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Figure 2-59. Stratix IOE Structure
Logic Array OE Register OE D Q
OE Register D Q
Output Register Output A D Q
CLK Output Register Output B D Q Input Register D Q
Input A Input B
Input Register D Q
Input Latch D ENA Q
The IOEs are located in I/O blocks around the periphery of the Stratix device. There are up to four IOEs per row I/O block and six IOEs per column I/O block. The row I/O blocks drive row, column, or direct link interconnects. The column I/O blocks drive column interconnects. Figure 2-60 shows how a row I/O block connects to the logic array. Figure 2-61 shows how a column I/O block connects to the logic array.
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Figure 2-60. Row I/O Block Connection to the Interconnect
R4, R8 & R24 Interconnects
C4, C8 & C16 Interconnects
I/O Interconnect I/O Block Local Interconnect 16 Control Signals from I/O Interconnect (1)
16
28 Data & Control Signals from Logic Array (2) 28 Horizontal I/O Block
LAB
io_dataouta[3..0] io_dataoutb[3..0]
Direct Link Interconnect to Adjacent LAB LAB Local Interconnect
Direct Link Interconnect to Adjacent LAB io_clk[7:0]
Horizontal I/O Block Contains up to Four IOEs
Notes to Figure 2-60:
(1) (2) The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0], four clocks io_clk[3..0], and four clear signals io_bclr[3..0]. The 28 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0], four output enables io_coe[3..0], four input clock enables io_cce_in[3..0], four output clock enables io_cce_out[3..0], four clocks io_cclk[3..0], and four clear signals io_cclr[3..0].
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Figure 2-61. Column I/O Block Connection to the Interconnect
42 Data & Control Signals from Logic Array (2)
Vertical I/O Block
Vertical I/O Block Contains up to Six IOEs
16 Control Signals from I/O Interconnect (1) I/O Block Local Interconnect
16
42 IO_datain[3:0]
io_clk[7..0]
I/O Interconnect
R4, R8 & R24 Interconnects
LAB
LAB
LAB
LAB Local Interconnect
C4, C8 & C16 Interconnects
Notes to Figure 2-61:
(1) (2) The 16 control signals are composed of four output enables io_boe[3..0], four clock enables io_bce[3..0], four clocks io_bclk[3..0], and four clear signals io_bclr[3..0]. The 42 data and control signals consist of 12 data out lines; six lines each for DDR applications io_dataouta[5..0] and io_dataoutb[5..0], six output enables io_coe[5..0], six input clock enables io_cce_in[5..0], six output clock enables io_cce_out[5..0], six clocks io_cclk[5..0], and six clear signals io_cclr[5..0].
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Stratix devices have an I/O interconnect similar to the R4 and C4 interconnect to drive high-fanout signals to and from the I/O blocks. There are 16 signals that drive into the I/O blocks composed of four output enables io_boe[3..0], four clock enables io_bce[3..0], four clocks io_bclk[3..0], and four clear signals io_bclr[3..0]. The pin's datain signals can drive the IO interconnect, which in turn drives the logic array or other I/O blocks. In addition, the control and data signals can be driven from the logic array, providing a slower but more flexible routing resource. The row or column IOE clocks, io_clk[7..0], provide a dedicated routing resource for low-skew, high-speed clocks. I/O clocks are generated from regional, global, or fast regional clocks (see "PLLs & Clock Networks" on page 2-73). Figure 2-62 illustrates the signal paths through the I/O block. Figure 2-62. Signal Path through the I/O Block
Row or Column io_clk[7..0] io_boe[3..0]
From I/O Interconnect
io_bce[3..0] io_bclk[3..0] io_bclr[3..0]
To Other IOEs
To Logic Array
io_datain0 io_datain1 oe ce_in ce_out io_coe io_cce_in io_cce_out Control Signal Selection aclr/apreset sclr/spreset clk_in io_cclr clk_out io_cclk io_dataout0 io_dataout1 IOE
From Logic Array
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Each IOE contains its own control signal selection for the following control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset, clk_in, and clk_out. Figure 2-63 illustrates the control signal selection. Figure 2-63. Control Signal Selection per IOE
io_bclk[3..0] Dedicated I/O Clock [7..0] I/O Interconnect [15..0] Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect io_coe io_bce[3..0] io_bclr[3..0] io_boe[3..0]
io_cclr
io_cce_out
io_cce_in
io_cclk
clk_out
ce_out
sclr/preset
clk_in
ce_in
aclr/preset
oe
In normal bidirectional operation, the input register can be used for input data requiring fast setup times. The input register can have its own clock input and clock enable separate from the OE and output registers. The output register can be used for data requiring fast clock-to-output performance. The OE register can be used for fast clock-to-output enable timing. The OE and output register share the same clock source and the same clock enable source from local interconnect in the associated LAB, dedicated I/O clocks, and the column and row interconnects. Figure 2-64 shows the IOE in bidirectional configuration.
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Figure 2-64. Stratix IOE in Bidirectional I/O Configuration Note (1)
Column or Row Interconnect ioe_clk[7..0]
I/O Interconnect [15..0]
OE OE Register D clkout ENA CLRN/PRN OE Register tCO Delay VCCIO Q Output tZX Delay
ce_out
Output Enable Clock Enable Delay Output Clock Enable Delay
Optional PCI Clamp
VCCIO
aclr/prn
Programmable Pull-Up Resistor
Chip-Wide Reset Output Register D Q Output Pin Delay Drive Strength Control Open-Drain Output Slew Control Input Pin to Logic Array Delay Input Pin to Input Register Delay
Logic Array to Output Register Delay sclr/preset
ENA CLRN/PRN
Bus-Hold Circuit
Input Register clkin ce_in Input Clock Enable Delay D Q
ENA CLRN/PRN
Note to Figure 2-64:
(1) All input signals to the IOE can be inverted at the IOE.
The Stratix device IOE includes programmable delays that can be activated to ensure zero hold times, input IOE register-to-logic array register transfers, or logic array-to-output IOE register transfers. A path in which a pin directly drives a register may require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinatorial logic may not require the delay. Programmable delays exist for decreasing input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can program these delays to automatically minimize setup time while providing a zero hold time. Programmable delays can increase the register-to-pin delays for output
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and/or output enable registers. A programmable delay exists to increase the tZX delay to the output pin, which is required for ZBT interfaces. Table 2-24 shows the programmable delays for Stratix devices.
Table 2-24. Stratix Programmable Delay Chain Programmable Delays
Input pin to logic array delay Input pin to input register delay Output pin delay Output enable register tCO delay Output tZX delay Output clock enable delay Input clock enable delay Logic array to output register delay Output enable clock enable delay
Quartus II Logic Option
Decrease input delay to internal cells Decrease input delay to input register Increase delay to output pin Increase delay to output enable pin Increase tZX delay to output pin Increase output clock enable delay Increase input clock enable delay Decrease input delay to output register Increase output enable clock enable delay
The IOE registers in Stratix devices share the same source for clear or preset. You can program preset or clear for each individual IOE. You can also program the registers to power up high or low after configuration is complete. If programmed to power up low, an asynchronous clear can control the registers. If programmed to power up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of another device's active-low input upon power-up. If one register in an IOE uses a preset or clear signal then all registers in the IOE must use that same signal if they require preset or clear. Additionally a synchronous reset signal is available for the IOE registers.
Double-Data Rate I/O Pins
Stratix devices have six registers in the IOE, which support DDR interfacing by clocking data on both positive and negative clock edges. The IOEs in Stratix devices support DDR inputs, DDR outputs, and bidirectional DDR modes. When using the IOE for DDR inputs, the two input registers clock double rate input data on alternating edges. An input latch is also used within the IOE for DDR input acquisition. The latch holds the data that is present during the clock high times. This allows both bits of data to be synchronous with the same clock edge (either rising or falling). Figure 2-65 shows an IOE configured for DDR input. Figure 2-66 shows the DDR input timing diagram.
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Figure 2-65. Stratix IOE in DDR Input I/O Configuration Note (1)
Column or Row Interconnect VCCIO ioe_clk[7..0] (1) DQS Local Bus (1), (2) To DQS Local Bus (3)
Optional PCI Clamp
VCCIO
I/O Interconnect [15..0] (1)
Programmable Pull-Up Resistor
Input Pin to Input Register Delay sclr Input Register D clkin ENA CLRN/PRN Q
Output Clock Enable Delay aclr/prn
Bus-Hold Circuit
Chip-Wide Reset Input Register D Q D Latch Q
ENA CLRN/PRN
ENA CLRN/PRN
Notes to Figure 2-65:
(1) (2) (3) All input signals to the IOE can be inverted at the IOE. This signal connection is only allowed on dedicated DQ function pins. This signal is for dedicated DQS function pins only.
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Figure 2-66. Input Timing Diagram in DDR Mode
Data at input pin A0 B1 A1 B2 A2 B3 A3 B4
CLK
A'
A1
A2
A3
Input To Logic Array
B' B1 B2 B3
When using the IOE for DDR outputs, the two output registers are configured to clock two data paths from LEs on rising clock edges. These output registers are multiplexed by the clock to drive the output pin at a x2 rate. One output register clocks the first bit out on the clock high time, while the other output register clocks the second bit out on the clock low time. Figure 2-67 shows the IOE configured for DDR output. Figure 2-68 shows the DDR output timing diagram.
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Figure 2-67. Stratix IOE in DDR Output I/O Configuration Notes (1), (2)
Column or Row Interconnect IOE_CLK[7..0]
I/O Interconnect [15..0]
OE Register D clkout ENA CLRN/PRN Output Enable Clock Enable Delay Output Clock Enable Delay aclr/prn VCCIO Q Output tZX Delay
OE Register tCO Delay
Chip-Wide Reset
OE Register D sclr ENA CLRN/PRN Q
Optional PCI Clamp
VCCIO
Used for DDR SDRAM
Programmable Pull-Up Resistor
Logic Array to Output Register Delay
Output Register D Q Output Pin Delay ENA CLRN/PRN clk
Logic Array to Output Register Delay
Output Register D Q
Drive Strength Control Open-Drain Output Slew Control
ENA CLRN/PRN
Bus-Hold Circuit
Notes to Figure 2-67:
(1) (2) All input signals to the IOE can be inverted at the IOE. The tristate is by default active high. It can, however, be designed to be active low.
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Figure 2-68. Output Timing Diagram in DDR Mode
CLK
A From Internal Registers B
A1
A2
A3
A4
B1
B2
B3
B4
DDR output
B1
A1
B2
A2
B3
A3
The Stratix IOE operates in bidirectional DDR mode by combining the DDR input and DDR output configurations. Stratix device I/O pins transfer data on a DDR bidirectional bus to support DDR SDRAM. The negative-edge-clocked OE register holds the OE signal inactive until the falling edge of the clock. This is done to meet DDR SDRAM timing requirements.
External RAM Interfacing
Stratix devices support DDR SDRAM at up to 200 MHz (400-Mbps data rate) through dedicated phase-shift circuitry, QDR and QDRII SRAM interfaces up to 167 MHz, and ZBT SRAM interfaces up to 200 MHz. Stratix devices also provide preliminary support for reduced latency DRAM II (RLDRAM II) at rates up to 200 MHz through the dedicated phase-shift circuitry. 1 In addition to the required signals for external memory interfacing, Stratix devices offer the optional clock enable signal. By default the Quartus II software sets the clock enable signal high, which tells the output register to update with new values. The output registers hold their own values if the design sets the clock enable signal low. See Figure 2-64.
f
To find out more about the DDR SDRAM specification, see the JEDEC web site (www.jedec.org). For information on memory controller megafunctions for Stratix devices, see the Altera web site (www.altera.com). See AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices for more information on DDR SDRAM interface in Stratix. Also see AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices and AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices.
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Tables 2-25 and 2-26 show the performance specification for DDR SDRAM, RLDRAM II, QDR SRAM, QDRII SRAM, and ZBT SRAM interfaces in EP1S10 through EP1S40 devices and in EP1S60 and EP1S80 devices. The DDR SDRAM and QDR SRAM numbers in Table 2-25 have been verified with hardware characterization with third-party DDR SDRAM and QDR SRAM devices over temperature and voltage extremes.
Table 2-25. External RAM Support in EP1S10 through EP1S40 Devices Maximum Clock Rate (MHz) DDR Memory Type I/O Standard -5 Speed Grade -6 Speed Grade WireBond
133 110 (5) 133 133 200
-7 Speed Grade FlipChip
133 133 (5) 133 133 167
-8 Speed Grade FlipChip
100 100 (5) 100 100 133
Flip-Chip Flip-Chip
DDR SDRAM (1), (2) DDR SDRAM - side banks (2), (3), (4) RLDRAM II (4) QDR SRAM (6) QDRII SRAM (6) ZBT SRAM (7) Notes to Table 2-25:
(1) (2) (3) (4) (5) (6) (7)
WireBond
100 100 (5) 100 100 167
WireBond
100 100 (5) 100 100 133
SSTL-2 SSTL-2 1.8-V HSTL 1.5-V HSTL 1.5-V HSTL LVTTL
200 150 200 167 200 200
167 133 (5) 167 167 200
These maximum clock rates apply if the Stratix device uses DQS phase-shift circuitry to interface with DDR SDRAM. DQS phase-shift circuitry is only available in the top and bottom I/O banks (I/O banks 3, 4, 7, and 8). For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. DDR SDRAM is supported on the Stratix device side I/O banks (I/O banks 1, 2, 5, and 6) without dedicated DQS phase-shift circuitry. The read DQS signal is ignored in this mode. These performance specifications are preliminary. This device does not support RLDRAM II. For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices. For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices.
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Table 2-26. External RAM Support in EP1S60 & EP1S80 Devices Maximum Clock Rate (MHz) DDR Memory Type
DDR SDRAM (1), (2)
I/O Standard -5 Speed Grade
SSTL-2 167 150 133 167 200
-6 Speed Grade
167 133 133 167 200
-7 Speed Grade
133 133 133 133 167
DDR SDRAM - side banks (2), (3) SSTL-2 QDR SRAM (4) QDRII SRAM (4) ZBT SRAM (5) Notes to Table 2-26:
(1) (2) (3) (4) (5)
1.5-V HSTL 1.5-V HSTL LVTTL
These maximum clock rates apply if the Stratix device uses DQS phase-shift circuitry to interface with DDR SDRAM. DQS phase-shift circuitry is only available in the top and bottom I/O banks (I/O banks 3, 4, 7, and 8). For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices. DDR SDRAM is supported on the Stratix device side I/O banks (I/O banks 1, 2, 5, and 6) without dedicated DQS phase-shift circuitry. The read DQS signal is ignored in this mode. Numbers are preliminary. For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Reference Design for Stratix & Stratix GX Devices. For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX Devices.
In addition to six I/O registers and one input latch in the IOE for interfacing to these high-speed memory interfaces, Stratix devices also have dedicated circuitry for interfacing with DDR SDRAM. In every Stratix device, the I/O banks at the top (I/O banks 3 and 4) and bottom (I/O banks 7 and 8) of the device support DDR SDRAM up to 200 MHz. These pins support DQS signals with DQ bus modes of x8, x16, or x32. Table 2-27 shows the number of DQ and DQS buses that are supported per device.
Table 2-27. DQS & DQ Bus Mode Support Device
EP1S10
(Part 1 of 2) Note (1) Number of x8 Groups
12 (2) 16 (3) 18(4) 16(3) 20
Package
672-pin BGA 672-pin FineLine BGA 484-pin FineLine BGA 780-pin FineLine BGA
Number of x16 Groups
0 0 7 (5) 7 (5) 7 (5)
Number of x32 Groups
0 4 4 4 4
EP1S20
484-pin FineLine BGA 672-pin BGA 672-pin FineLine BGA 780-pin FineLine BGA
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Table 2-27. DQS & DQ Bus Mode Support Device
EP1S25
(Part 2 of 2) Note (1) Number of x8 Groups
16 (3) 20 20
Package
672-pin BGA 672-pin FineLine BGA 780-pin FineLine BGA 1,020-pin FineLine BGA
Number of x16 Groups
8 8 8
Number of x32 Groups
4 4 4
EP1S30
956-pin BGA 780-pin FineLine BGA 1,020-pin FineLine BGA 956-pin BGA 1,020-pin FineLine BGA 1,508-pin FineLine BGA 956-pin BGA 1,020-pin FineLine BGA 1,508-pin FineLine BGA 956-pin BGA 1,508-pin FineLine BGA 1,923-pin FineLine BGA
EP1S40
20
8
4
EP1S60
20
8
4
EP1S80
20
8
4
Notes to Table 2-27:
(1) (2) (3) (4) (5) See the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2 for VREF guidelines. These packages have six groups in I/O banks 3 and 4 and six groups in I/O banks 7 and 8. These packages have eight groups in I/O banks 3 and 4 and eight groups in I/O banks 7 and 8. This package has nine groups in I/O banks 3 and 4 and nine groups in I/O banks 7 and 8. These packages have three groups in I/O banks 3 and 4 and four groups in I/O banks 7 and 8.
A compensated delay element on each DQS pin automatically aligns input DQS synchronization signals with the data window of their corresponding DQ data signals. The DQS signals drive a local DQS bus in the top and bottom I/O banks. This DQS bus is an additional resource to the I/O clocks and is used to clock DQ input registers with the DQS signal. Two separate single phase-shifting reference circuits are located on the top and bottom of the Stratix device. Each circuit is driven by a system reference clock through the CLK pins that is the same frequency as the DQS signal. Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed the phase-shift circuitry on the bottom of the device. The phase-shifting reference circuit on the top of the device controls the compensated delay elements for all 10 DQS pins located at the top of the device. The phase-shifting reference circuit on the bottom of the device controls the compensated delay elements for all 10 DQS pins located on the bottom of the device. All 10 delay elements (DQS signals) on either the top or bottom of the device
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shift by the same degree amount. For example, all 10 DQS pins on the top of the device can be shifted by 90 and all 10 DQS pins on the bottom of the device can be shifted by 72. The reference circuits require a maximum of 256 system reference clock cycles to set the correct phase on the DQS delay elements. Figure 2-69 illustrates the phase-shift reference circuit control of each DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device. Figure 2-69. Simplified Diagram of the DQS Phase-Shift Circuitry
Input Reference Clock
Phase Comparator
Up/Down Counter
Delay Chains
6
Control Signals to DQS Pins
See the External Memory Interfaces chapter in the Stratix Device Handbook, Volume 2 for more information on external memory interfaces.
Programmable Drive Strength
The output buffer for each Stratix device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL and LVCMOS standard has several levels of drive strength that the user can control. SSTL-3 Class I and II, SSTL-2 Class I and II, HSTL Class I and II, and 3.3-V GTL+ support a minimum setting, the lowest drive strength that guarantees the IOH/IOL of the standard. Using minimum settings provides signal slew rate control to reduce system noise and signal overshoot.
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Table 2-28 shows the possible settings for the I/O standards with drive strength control.
Table 2-28. Programmable Drive Strength I/O Standard
3.3-V LVTTL 3.3-V LVCMOS 2.5-V LVTTL/LVCMOS 1.8-V LVTTL/LVCMOS 1.5-V LVCMOS GTL/GTL+ 1.5-V HSTL Class I and II 1.8-V HSTL Class I and II SSTL-3 Class I and II SSTL-2 Class I and II SSTL-18 Class I and II Notes to Table 2-28:
(1) (2) This is the Quartus II software default current setting. I/O banks 1, 2, 5, and 6 do not support this setting.
IOH / IOL Current Strength Setting (mA)
24 (1), 16, 12, 8, 4 24 (2), 12 (1), 8, 4, 2 16 (1), 12, 8, 2 12 (1), 8, 2 8 (1), 4, 2 Support max and min strength
Quartus II software version 4.2 and later will report current strength as "PCI Compliant" for 3.3-V PCI, 3.3-V PCI-X 1.0, and Compact PCI I/O standards. Stratix devices support series on-chip termination (OCT) using programmable drive strength. For more information, contact your Altera Support Representative.
Open-Drain Output
Stratix devices provide an optional open-drain (equivalent to an opencollector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (e.g., interrupt and writeenable signals) that can be asserted by any of several devices.
Slew-Rate Control
The output buffer for each Stratix device I/O pin has a programmable output slew-rate control that can be configured for low-noise or highspeed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these fast transitions may introduce noise transients into the system. A slow slew rate reduces system noise, but adds a nominal delay to rising and falling edges. Each
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I/O pin has an individual slew-rate control, allowing you to specify the slew rate on a pin-by-pin basis. The slew-rate control affects both the rising and falling edges.
Bus Hold
Each Stratix device I/O pin provides an optional bus-hold feature. The bus-hold circuitry can weakly hold the signal on an I/O pin at its lastdriven state. Since the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not needed to hold a signal level when the bus is tri-stated. Table 2-29 shows bus hold support for different pin types.
Table 2-29. Bus Hold Support Pin Type
I/O pins
Bus Hold v
CLK[15..0] CLK[0,1,2,3,8,9,10,11] FCLK FPLL[7..10]CLK
v
The bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. You can select this feature individually for each I/O pin. The bus-hold output drives no higher than VCCIO to prevent overdriving signals. If the bus-hold feature is enabled, the programmable pull-up option cannot be used. Disable the bus-hold feature when using opendrain outputs with the GTL+ I/O standard or when the I/O pin has been configured for differential signals. The bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately 7 k to weakly pull the signal level to the last-driven state. See the DC & Switching Characteristics chapter of the Stratix Device Handbook, Volume 1 for the specific sustaining current driven through this resistor and overdrive current used to identify the next-driven input level. This information is provided for each VCCIO voltage level. The bus-hold circuitry is active only after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration.
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Programmable Pull-Up Resistor
Each Stratix device I/O pin provides an optional programmable pull-up resistor during user mode. If this feature is enabled for an I/O pin, the pull-up resistor (typically 25 k) weakly holds the output to the VCCIO level of the output pin's bank. Table 2-30 shows which pin types support the weak pull-up resistor feature.
Table 2-30. Programmable Weak Pull-Up Resistor Support Pin Type
I/O pins
Programmable Weak Pull-Up Resistor v
v
CLK[15..0] FCLK FPLL[7..10]CLK
Configuration pins JTAG pins Note to Table 2-30:
(1) TDO pins do not support programmable weak pull-up resistors.
v (1)
Advanced I/O Standard Support
Stratix device IOEs support the following I/O standards:

LVTTL LVCMOS 1.5 V 1.8 V 2.5 V 3.3-V PCI 3.3-V PCI-X 1.0 3.3-V AGP (1x and 2x) LVDS LVPECL 3.3-V PCML HyperTransport Differential HSTL (on input/output clocks only) Differential SSTL (on output column clock pins only) GTL/GTL+ 1.5-V HSTL Class I and II
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1.8-V HSTL Class I and II SSTL-3 Class I and II SSTL-2 Class I and II SSTL-18 Class I and II CTT
Table 2-31 describes the I/O standards supported by Stratix devices.
Table 2-31. Stratix Supported I/O Standards Input Reference Voltage (VREF) (V)
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.75 1.25 0.8 1.0 0.75 0.9 0.90 1.25 1.5 1.32 1.5
I/O Standard
Type
Output Supply Voltage (VCCIO) (V)
3.3 3.3 2.5 1.8 1.5 3.3 3.3 3.3 3.3 3.3 2.5 1.5 2.5 N/A N/A 1.5 1.8 1.8 2.5 3.3 3.3 3.3
Board Termination Voltage (VTT) (V)
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.75 1.25 1.20 1.5 0.75 0.9 0.90 1.25 1.5 N/A 1.5
LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X 1.0 LVDS LVPECL 3.3-V PCML HyperTransport Differential HSTL (1) Differential SSTL (2) GTL GTL+ 1.5-V HSTL Class I and II 1.8-V HSTL Class I and II SSTL-18 Class I and II SSTL-2 Class I and II SSTL-3 Class I and II AGP (1x and 2 ) CTT Notes to Table 2-31:
(1) (2)
Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Single-ended Differential Differential Differential Differential Differential Differential Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced Voltage-referenced
This I/O standard is only available on input and output clock pins. This I/O standard is only available on output column clock pins.
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f
For more information on I/O standards supported by Stratix devices, see the Selectable I/O Standards in Stratix & Stratix GX Devices chapter of the Stratix Device Handbook, Volume 2. Stratix devices contain eight I/O banks in addition to the four enhanced PLL external clock out banks, as shown in Figure 2-70. The four I/O banks on the right and left of the device contain circuitry to support highspeed differential I/O for LVDS, LVPECL, 3.3-V PCML, and HyperTransport inputs and outputs. These banks support all I/O standards listed in Table 2-31 except PCI I/O pins or PCI-X 1.0, GTL, SSTL-18 Class II, and HSTL Class II outputs. The top and bottom I/O banks support all single-ended I/O standards. Additionally, Stratix devices support four enhanced PLL external clock output banks, allowing clock output capabilities such as differential support for SSTL and HSTL. Table 2-32 shows I/O standard support for each I/O bank.
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Figure 2-70. Stratix I/O Banks Notes (1), (2), (3)
DQS9T
PLL7
DQS8T
DQS7T
Bank 3
DQS6T
DQS5T 9
VREF1B3 VREF2B3 VREF3B3 VREF4B3 VREF5B3
PLL5 10
DQS4T PLL11
DQS3T
DQS2T
Bank 4
DQS1T
DQS0T
VREF1B4 VREF2B4 VREF3B4 VREF4B4 VREF5B4 PLL10
VREF1B2 VREF2B2 VREF3B2 VREF4B2
LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4)
Bank 2
LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4) I/O Banks 3, 4, 9 & 10 Support All Single-Ended I/O Standards (5)
Bank 5 Bank 6
(5)
PLL1
PLL2 VREF1B1 VREF2B1 VREF3B1 VREF4B1
Bank 1
(5) LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4)
I/O Banks 7, 8, 11 & 12 Support All Single-Ended I/O Standards LVDS, LVPECL, 3.3-V PCML, and HyperTransport I/O Block and Regular I/O Pins (4)
(5)
Bank 8
PLL8 VREF5B8 VREF4B8 VREF3B8 VREF2B8 VREF1B8
11 DQS6B DQS5B
12 PLL12 DQS4B DQS3B
Bank 7
VREF5B7 VREF4B7 VREF3B7 VREF2B7 VREF1B7 PLL9
DQS9B
DQS8B
DQS7B
PLL6
DQS2B
DQS1B
DQS0B
Notes to Figure 2-70:
(1) (2) (3) (4) (5) Figure 2-70 is a top view of the silicon die. This will correspond to a top-down view for non-flip-chip packages, but will be a reverse view for flip-chip packages. Figure 2-70 is a graphic representation only. See the device pin-outs on the web (www.altera.com) and the Quartus II software for exact locations. Banks 9 through 12 are enhanced PLL external clock output banks. If the high-speed differential I/O pins are not used for high-speed differential signaling, they can support all of the I/O standards except HSTL Class I and II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and AGP 1x /2x . For guidelines for placing single-ended I/O pads next to differential I/O pads, see the Selectable I/O Standards in Stratix and Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2.
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VREF4B6 VREF3B6 VREF2B6 VREF1B6
I/O Banks 1, 2, 5, and 6 Support All Single-Ended I/O Standards Except Differential HSTL Output Clocks, Differential SSTL-2 Output Clocks, HSTL Class II, GTL, SSTL-18 Class II, PCI, PCI-X 1.0, and AGP 1x/2x
PLL4
PLL3
VREF4B5 VREF3B5 VREF2B5 VREF1B5
I/O Structure
Table 2-32 shows I/O standard support for each I/O bank.
Table 2-32. I/O Support by Bank (Part 1 of 2) I/O Standard
LVTTL LVCMOS 2.5 V 1.8 V 1.5 V 3.3-V PCI 3.3-V PCI-X 1.0 LVPECL 3.3-V PCML LVDS HyperTransport technology Differential HSTL (clock inputs) Differential HSTL (clock outputs) Differential SSTL (clock outputs) 3.3-V GTL 3.3-V GTL+ 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II SSTL-18 Class I SSTL-18 Class II SSTL-2 Class I SSTL-2 Class II SSTL-3 Class I
Top & Bottom Banks (3, 4, 7 & 8) v v v v v v v
Left & Right Banks (1, 2, 5 & 6) v v v v v
Enhanced PLL External Clock Output Banks (9, 10, 11 & 12) v v v v v v v
v v v v v v
v v v v
v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v v
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Table 2-32. I/O Support by Bank (Part 2 of 2) I/O Standard
SSTL-3 Class II AGP (1x and 2x ) CTT
Top & Bottom Banks (3, 4, 7 & 8) v v v
Left & Right Banks (1, 2, 5 & 6) v v
Enhanced PLL External Clock Output Banks (9, 10, 11 & 12) v v v
Each I/O bank has its own VCCIO pins. A single device can support 1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different standard independently. Each bank also has dedicated VREF pins to support any one of the voltage-referenced standards (such as SSTL-3) independently. Each I/O bank can support multiple standards with the same VCCIO for input and output pins. Each bank can support one voltage-referenced I/O standard. For example, when VCCIO is 3.3 V, a bank can support LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
Differential On-Chip Termination
Stratix devices provide differential on-chip termination (LVDS I/O standard) to reduce reflections and maintain signal integrity. Differential on-chip termination simplifies board design by minimizing the number of external termination resistors required. Termination can be placed inside the package, eliminating small stubs that can still lead to reflections. The internal termination is designed using transistors in the linear region of operation. Stratix devices support internal differential termination with a nominal resistance value of 137.5 for LVDS input receiver buffers. LVPECL signals require an external termination resistor. Figure 2-71 shows the device with differential termination.
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Figure 2-71. LVDS Input Differential On-Chip Termination
Transmitting Device Receiving Device with Differential Termination
Z0
+
RD Z0
+
I/O banks on the left and right side of the device support LVDS receiver (far-end) differential termination. Table 2-33 shows the Stratix device differential termination support.
Table 2-33. Differential Termination Supported by I/O Banks Differential Termination Support
Differential termination (1), (2) Notes to Table 2-33:
(1) (2) Clock pin CLK0, CLK2, CLK9, CLK11, and pins FPLL[7..10]CLK do not support differential termination. Differential termination is only supported for LVDS because of a 3.3-V VC C I O .
I/O Standard Support
LVDS
Top & Bottom Banks (3, 4, 7 & 8)
Left & Right Banks (1, 2, 5 & 6)
v
Table 2-34 shows the termination support for different pin types.
Table 2-34. Differential Termination Support Across Pin Types Pin Type
Top and bottom I/O banks (3, 4, 7, and 8)
RD
v v
DIFFIO_RX[] CLK[0,2,9,11],CLK[4-7],CLK[12-15] CLK[1,3,8,10] FCLK FPLL[7..10]CLK
The differential on-chip resistance at the receiver input buffer is 118 20 %.
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However, there is additional resistance present between the device ball and the input of the receiver buffer, as shown in Figure 2-72. This resistance is because of package trace resistance (which can be calculated as the resistance from the package ball to the pad) and the parasitic layout metal routing resistance (which is shown between the pad and the intersection of the on-chip termination and input buffer). Figure 2-72. Differential Resistance of LVDS Differential Pin Pair (RD)
Package Ball
0.3 RD
Pad
9.3
LVDS Input Buffer
0.3
9.3
Differential On-Chip Termination Resistor
Table 2-35 defines the specification for internal termination resistance for commercial devices.
Table 2-35. Differential On-Chip Termination Resistance Symbol
RD (2)
Description
Internal differential termination for LVDS
Conditions Min
Commercial (1), (3) Industrial (2), (3) 110 100
Unit Typ
135 135
Max
165 170 W W
Notes to Table 2-35:
(1) (2) (3) Data measured over minimum conditions (Tj = 0 C, VC C I O +5%) and maximum conditions (Tj = 85 C, VC C I O = -5%). Data measured over minimum conditions (Tj = -40 C, VCCIO +5%) and maximum conditions (Tj = 100 C, VCCIO = -5%). LVDS data rate is supported for 840 Mbps using internal differential termination.
MultiVolt I/O Interface
The Stratix architecture supports the MultiVolt I/O interface feature, which allows Stratix devices in all packages to interface with systems of different supply voltages. The Stratix VCCINT pins must always be connected to a 1.5-V power supply. With a 1.5-V VCCINT level, input pins are 1.5-V, 1.8-V, 2.5-V, and 3.3-V tolerant. The VCCIO pins can be connected to either a 1.5-V, 1.8-V, 2.5-V, or 3.3-V power supply, depending on the output requirements.
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High-Speed Differential I/O Support
The output levels are compatible with systems of the same voltage as the power supply (i.e., when VCCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems). When VCCIO pins are connected to a 3.3-V power supply, the output high is 3.3 V and is compatible with 3.3-V or 5.0-V systems. Table 2-36 summarizes Stratix MultiVolt I/O support.
Table 2-36. Stratix MultiVolt I/O Support Note (1) Input Signal (5) VCCIO (V)
1.5 1.8 2.5 3.3 Notes to Table 2-36:
(1) (2) (3) (4) (5) (6) To drive inputs higher than VCCIO but less than 4.1 V, disable the PCI clamping diode. However, to drive 5.0-V inputs to the device, enable the PCI clamping diode to prevent VI from rising above 4.0 V. The input pin current may be slightly higher than the typical value. Although VCCIO specifies the voltage necessary for the Stratix device to drive out, a receiving device powered at a different level can still interface with the Stratix device if it has inputs that tolerate the VCCIO value. Stratix devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode. This is the external signal that is driving the Stratix device. This represents the system voltage that Stratix supports when a VCCIO pin is connected to a specific voltage level. For example, when VCCIO is 3.3 V and if the I/O standard is LVTTL/LVCMOS, the output high of the signal coming out from Stratix is 3.3 V and is compatible with 3.3-V or 5.0-V systems.
Output Signal (6) 5.0 V 1.5 V v v (3) v (3) v (4) v (3) v v (3) v (3) v v (3) v v 1.8 V 2.5 V 3.3 V 5.0 V
1.5 V v v (2)
1.8 V v v
2.5 V v (2) v (2) v v (2)
3.3 V v (2) v (2) v v
High-Speed Differential I/O Support
Stratix devices contain dedicated circuitry for supporting differential standards at speeds up to 840 Mbps. The following differential I/O standards are supported in the Stratix device: LVDS, LVPECL, HyperTransport, and 3.3-V PCML. There are four dedicated high-speed PLLs in the EP1S10 to EP1S25 devices and eight dedicated high-speed PLLs in the EP1S30 to EP1S80 devices to multiply reference clocks and drive high-speed differential SERDES channels.
f
See the Stratix device pin-outs at www.altera.com for additional high speed DIFFIO pin information for Stratix devices.
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Stratix Architecture
Table 2-37 shows the number of channels that each fast PLL can clock in EP1S10, EP1S20, and EP1S25 devices. Tables 2-38 through Table 2-41 show this information for EP1S30, EP1S40, EP1S60, and EP1S80 devices.
Table 2-37. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 1 of 2) Note (1) Device
EP1S10
Package
Transmitter/ Receiver
Total Channels
20
Maximum Speed (Mbps)
840 (4) 840 (3)
Center Fast PLLs PLL 1
5 10 5 10 9 18 9 18 11 22 11 22 6 12 5 10 12 24 13 25 17 33 17 33
PLL 2
5 10 5 10 9 18 9 18 11 22 11 22 6 12 5 10 12 24 12 25 16 33 16 33
PLL 3
5 10 5 10 9 18 9 18 11 22 11 22 6 12 5 10 12 24 12 25 16 33 16 33
PLL 4
5 10 5 10 9 18 9 18 11 22 11 22 6 12 5 10 12 24 13 25 17 33 17 33
484-pin FineLine BGA Transmitter (2)
Receiver
20
840 (4) 840 (3)
672-pin FineLine BGA Transmitter (2) 672-pin BGA Receiver
36
624 (4) 624 (3)
36
624 (4) 624 (3)
780-pin FineLine BGA Transmitter (2)
44
840 (4) 840 (3)
Receiver
44
840 (4) 840 (3)
EP1S20
484-pin FineLine BGA Transmitter (2)
24
840 (4) 840 (3)
Receiver
20
840 (4) 840 (3)
672-pin FineLine BGA Transmitter (2) 672-pin BGA Receiver
48
624 (4) 624 (3)
50
624 (4) 624 (3)
780-pin FineLine BGA Transmitter (2)
66
840 (4) 840 (3)
Receiver
66
840 (4) 840 (3)
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High-Speed Differential I/O Support
Table 2-37. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 2 of 2) Note (1) Device
EP1S25
Package
Transmitter/ Receiver
Total Channels
56
Maximum Speed (Mbps)
624 (4) 624 (3)
Center Fast PLLs PLL 1
14 28 14 29 18 35 17 33 19 39 19 39
PLL 2
14 28 15 29 17 35 16 33 20 39 20 39
PLL 3
14 28 15 29 17 35 16 33 20 39 20 39
PLL 4
14 28 14 29 18 35 17 33 19 39 19 39
672-pin FineLine BGA Transmitter (2) 672-pin BGA Receiver
58
624 (4) 624 (3)
780-pin FineLine BGA Transmitter (2)
70
840 (4) 840 (3)
Receiver
66
840 (4) 840 (3)
1,020-pin FineLine BGA
Transmitter (2)
78
840 (4) 840 (3)
Receiver
78
840 (4) 840 (3)
Notes to Table 2-37:
(1) The first row for each transmitter or receiver reports the number of channels driven directly by the PLL. The second row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center PLL. For example, in the 484-pin FineLine BGA EP1S10 device, PLL 1 can drive a maximum of five channels at 840 Mbps or a maximum of 10 channels at 840 Mbps. The Quartus II software may also merge receiver and transmitter PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive both the maximum numbers of receiver and transmitter channels. The number of channels listed includes the transmitter clock output (tx_outclock) channel. If the design requires a DDR clock, it can use an extra data channel. These channels span across two I/O banks per side of the device. When a center PLL clocks channels in the opposite bank on the same side of the device it is called cross-bank PLL support. Both center PLLs can clock cross-bank channels simultaneously if, for example, PLL_1 is clocking all receiver channels and PLL_2 is clocking all transmitter channels. You cannot have two adjacent PLLs simultaneously clocking cross-bank receiver channels or two adjacent PLLs simultaneously clocking transmitter channels. Cross-bank allows for all receiver channels on one side of the device to be clocked on one clock while all transmitter channels on the device are clocked on the other center PLL. Crossbank PLLs are supported at full-speed, 840 Mbps. For wire-bond devices, the full-speed is 624 Mbps. These values show the channels available for each PLL without crossing another bank.
(2) (3)
(4)
When you span two I/O banks using cross-bank support, you can route only two load enable signals total between the PLLs. When you enable rx_data_align, you use both rxloadena and txloadena of a PLL. That leaves no loadena for the second PLL.
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Stratix Architecture
The only way you can use the rx_data_align is if one of the following is true:

The receiver PLL is only clocking receive channels (no resources for the transmitter) If all channels can fit in one I/O bank
Table 2-38. EP1S30 Differential Channels Note (1) Package
780-pin FineLine BGA
Transmitter Total /Receiver Channels
Transmitter (4) Receiver 70
Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed (Mbps) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
840 840 (5) 18 35 17 33 19 39 20 40 19 (1) 39 (1) 20 40 17 35 16 33 20 39 20 40 20 39 (1) 20 40 17 35 16 33 20 39 20 40 20 39 (1) 20 40 18 35 17 33 19 39 20 40 19 (1) 39 (1) 20 40 (6) (6) (6) (6) 20 20 19 19 20 20 19 (1) 19 (1) (6) (6) (6) (6) 20 20 20 20 20 20 20 20 (6) (6) (6) (6) 20 20 20 20 20 20 20 20 (6) (6) (6) (6) 20 20 19 19 20 20 19 (1) 19 (1)
66
840 840 (5)
956-pin BGA
Transmitter (4) Receiver
80
840 840 (5)
80
840 840 (5)
1,020-pin FineLine BGA
Transmitter (4)
80 (2) (7)
840 840 (5),(8)
Receiver
80 (2) (7)
840 840 (5),(8)
Table 2-39. EP1S40 Differential Channels (Part 1 of 2) Note (1) Package
780-pin FineLine BGA
Transmitter/ Total Receiver Channels
Transmitter (4) Receiver 68
Maximum Speed (Mbps)
840 840 (5)
Center Fast PLLs
Corner Fast PLLs (2), (3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
18 34 17 33 16 34 16 33 16 34 16 33 18 34 17 33 (6) (6) (6) (6) (6) (6) (6) (6) (6) (6) (6) (6) (6) (6) (6) (6)
66
840 840 (5)
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High-Speed Differential I/O Support
Table 2-39. EP1S40 Differential Channels (Part 2 of 2) Note (1) Package
956-pin BGA
Transmitter/ Total Receiver Channels
Transmitter (4) Receiver 80
Maximum Speed (Mbps)
840 840 (5)
Center Fast PLLs
Corner Fast PLLs (2), (3)
PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
18 35 20 40 18 (2) 35 (5) 20 40 18 (2) 35 (5) 20 40 17 35 20 40 17 (3) 35 (5) 20 40 17 (3) 35 (5) 20 40 17 35 20 40 17 (3) 35 (5) 20 40 17 (3) 35 (5) 20 40 18 35 20 40 18 (2) 35 (5) 20 40 18 (2) 35 (5) 20 40 20 20 18 18 20 20 18 (2) 18 (2) 20 20 18 (2) 18 (2) 20 20 17 17 20 20 17 (3) 17 (3) 20 20 17 (3) 17 (3) 20 20 17 17 20 20 17 (3) 17 (3) 20 20 17 (3) 17 (3) 20 20 18 18 20 20 18 (2) 18 (2) 20 20 18 (2) 18 (2)
80
840 840 (5)
1,020-pin FineLine BGA
Transmitter (4)
80 (10) (7)
840 840 (5), (8)
Receiver
80 (10) (7)
840 840 (5), (8)
1,508-pin FineLine BGA
Transmitter (4)
80 (10) (7)
840 840 (5), (8)
Receiver
80 (10) (7)
840 840 (5), (8)
Table 2-40. EP1S60 Differential Channels (Part 1 of 2) Note (1) Package
956-pin BGA
Transmitter/ Total Receiver Channels
Transmitter (4) Receiver 80
Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 (Mbps)
840 840 (5), (8) 12 22 20 40 10 22 20 40 10 22 20 40 12 22 20 40 20 20 12 12 20 20 10 10 20 20 10 10 20 20 12 12
80
840 840 (5), (8)
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Stratix Architecture
Table 2-40. EP1S60 Differential Channels (Part 2 of 2) Note (1) Package
1,020-pin FineLine BGA
Transmitter/ Total Receiver Channels
Transmitter (4) 80 (12) (7)
Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10 (Mbps)
840 840 (5), (8) 12 (2) 22 (6) 20 40 12 (8) 22 (18) 20 40 10 (4) 22 (6) 20 40 10 (10) 22 (18) 20 40 10 (4) 22 (6) 20 40 10 (10) 22 (18) 20 40 12 (2) 22 (6) 20 40 12 (8) 22 (18) 20 40 20 20 12 (8) 12 (8) 20 20 12 (8) 12 (8) 20 20 10 (10) 10 (10) 20 20 10 (10) 10 (10) 20 20 10 (10) 10 (10) 20 20 10 (10) 10 (10) 20 20 12 (8) 12 (8) 20 20 12 (8) 12 (8)
Receiver
80 (10) (7)
840 840 (5), (8)
1,508-pin FineLine BGA
Transmitter (4)
80 (36) (7)
840 840 (5),(8)
Receiver
80 (36) (7)
840 840 (5),(8)
Table 2-41. EP1S80 Differential Channels (Part 1 of 2) Note (1) Package
956-pin BGA
Transmitter/ Total Receiver Channels
Transmitter (4) Receiver 80 (40) (7) 80
Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed (Mbps) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
840 840 (5),(8) 840 840 (5),(8) 10 20 20 40 10 (2) 20 (6) 20 40 10 20 20 40 10 (4) 20 (6) 20 40 10 20 20 40 10 (4) 20 (6) 20 40 10 20 20 40 10 (2) 20 (6) 20 40 20 20 10 10 20 20 10 (2) 10 (2) 20 20 10 10 20 20 10 (3) 10 (3) 20 20 10 10 20 20 10 (3) 10 (3) 20 20 10 10 20 20 10 (2) 10 (2)
1,020-pin FineLine BGA
Transmitter (4)
92 (12) (7)
840 840 (5),(8)
Receiver
90 (10) (7)
840 840 (5),(8)
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High-Speed Differential I/O Support
Table 2-41. EP1S80 Differential Channels (Part 2 of 2) Note (1) Package
1,508-pin FineLine BGA
Transmitter/ Total Receiver Channels
Transmitter (4) 80 (72) (7)
Maximum Center Fast PLLs Corner Fast PLLs (2), (3) Speed (Mbps) PLL1 PLL2 PLL3 PLL4 PLL7 PLL8 PLL9 PLL10
840 840 (5),(8) 10 (10) 20 (20) 20 40 10 (10) 20 (20) 20 40 10 (10) 20 (20) 20 40 10 (10) 20 (20) 20 40 20 (8) 20 (8) 10 (14) 10 (14) 20 (8) 20 (8) 10 (14) 10 (14) 20 (8) 20 (8) 10 (14) 10 (14) 20 (8) 20 (8) 10 (14) 10 (14)
Receiver
80 (56) (7)
840 840 (5),(8)
Notes to Tables 2-38 through 2-41:
(1) The first row for each transmitter or receiver reports the number of channels driven directly by the PLL. The second row below it shows the maximum channels a PLL can drive if cross bank channels are used from the adjacent center PLL. For example, in the 780-pin FineLine BGA EP1S30 device, PLL 1 can drive a maximum of 18 transmitter channels at 840 Mbps or a maximum of 35 transmitter channels at 840 Mbps. The Quartus II software may also merge transmitter and receiver PLLs when a receiver is driving a transmitter. In this case, one fast PLL can drive both the maximum numbers of receiver and transmitter channels. Some of the channels accessible by the center fast PLL and the channels accessible by the corner fast PLL overlap. Therefore, the total number of channels is not the addition of the number of channels accessible by PLLs 1, 2, 3, and 4 with the number of channels accessible by PLLs 7, 8, 9, and 10. For more information on which channels overlap, see the Stratix device pin-outs at www.altera.com. The corner fast PLLs in this device support a data rate of 840 Mbps for channels labeled "high" speed in the device pin-outs at www.altera.com. The numbers of channels listed include the transmitter clock output (tx_outclock) channel. An extra data channel can be used if a DDR clock is needed. These channels span across two I/O banks per side of the device. When a center PLL clocks channels in the opposite bank on the same side of the device it is called cross-bank PLL support. Both center PLLs can clock cross-bank channels simultaneously if say PLL_1 is clocking all receiver channels and PLL_2 is clocking all transmitter channels. You cannot have two adjacent PLLs simultaneously clocking cross-bank receiver channels or two adjacent PLLs simultaneously clocking transmitter channels. Cross-bank allows for all receiver channels on one side of the device to be clocked on one clock while all transmitter channels on the device are clocked on the other center PLL. Crossbank PLLs are supported at full-speed, 840 Mbps. For wire-bond devices, the full-speed is 624 Mbps. PLLs 7, 8, 9, and 10 are not available in this device. The number in parentheses is the number of slow-speed channels, guaranteed to operate at up to 462 Mbps. These channels are independent of the high-speed differential channels. For the location of these channels, see the device pin-outs at www.altera.com. See the Stratix device pin-outs at www.altera.com. Channels marked "high" speed are 840 MBps and "low" speed channels are 462 MBps.
(2)
(3) (4) (5)
(6) (7)
(8)
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Stratix Architecture
The high-speed differential I/O circuitry supports the following high speed I/O interconnect standards and applications:

UTOPIA IV SPI-4 Phase 2 (POS-PHY Level 4) SFI-4 10G Ethernet XSBI RapidIO HyperTransport
Dedicated Circuitry
Stratix devices support source-synchronous interfacing with LVDS, LVPECL, 3.3-V PCML, or HyperTransport signaling at up to 840 Mbps. Stratix devices can transmit or receive serial channels along with a low-speed or high-speed clock. The receiving device PLL multiplies the clock by a integer factor W (W = 1 through 32). For example, a HyperTransport application where the data rate is 800 Mbps and the clock rate is 400 MHz would require that W be set to 2. The SERDES factor J determines the parallel data width to deserialize from receivers or to serialize for transmitters. The SERDES factor J can be set to 4, 7, 8, or 10 and does not have to equal the PLL clock-multiplication W value. For a J factor of 1, the Stratix device bypasses the SERDES block. For a J factor of 2, the Stratix device bypasses the SERDES block, and the DDR input and output registers are used in the IOE. See Figure 2-73. Figure 2-73. High-Speed Differential I/O Receiver / Transmitter Interface Example
R4, R8, and R24 Interconnect
8 840 Mbps + - 8 Data Dedicated Receiver Interface Local Interconnect Dedicated Transmitter Interface 8 + - 840 Mbps
Data
8x 105 MHz Fast PLL
rx_load_en
8x
tx_load_en Regional or global clock
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2-137 Stratix Device Handbook, Volume 1
High-Speed Differential I/O Support
An external pin or global or regional clock can drive the fast PLLs, which can output up to three clocks: two multiplied high-speed differential I/O clocks to drive the SERDES block and/or external pin, and a low-speed clock to drive the logic array. The Quartus II MegaWizard(R) Plug-In Manager only allows the implementation of up to 20 receiver or 20 transmitter channels for each fast PLL. These channels operate at up to 840 Mbps. The receiver and transmitter channels are interleaved such that each I/O bank on the left and right side of the device has one receiver channel and one transmitter channel per LAB row. Figure 2-74 shows the fast PLL and channel layout in EP1S10, EP1S20, and EP1S25 devices. Figure 2-75 shows the fast PLL and channel layout in the EP1S30 to EP1S80 devices. Figure 2-74. Fast PLL & Channel Layout in the EP1S10, EP1S20 or EP1S25 Devices Note (1)
Up to 20 Receiver and Transmitter Channels (2) Transmitter Receiver Up to 20 Receiver and Transmitter Channels (2) Transmitter Receiver
CLKIN
Fast PLL 1 (3) (3) Fast PLL 2
Fast PLL 4 Fast PLL 3
CLKIN
CLKIN
CLKIN
Transmitter Receiver Up to 20 Receiver and Transmitter Channels (2)
Transmitter Receiver Up to 20 Receiver and Transmitter Channels (2)
Notes to Figure 2-74:
(1) (2) (3) Wire-bond packages support up to 624 Mbps. See Table 2-41 for the number of channels each device supports. There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of its bank quadrant, those clocked channels support up to 840 Mbps for "high" speed channels and 462 Mbps for "low" speed channels, as labeled in the device pin-outs at www.altera.com.
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Stratix Architecture
Figure 2-75. Fast PLL & Channel Layout in the EP1S30 to EP1S80 Devices Note (1)
FPLL7CLK Fast PLL 7 Fast PLL 10 FPLL10CLK
Transmitter Receiver
Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (2)
Transmitter Receiver
Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (2)
Transmitter Receiver Transmitter Receiver
CLKIN CLKIN
Fast PLL 1 Fast PLL 2
(3)
(3)
Fast PLL 4 Fast PLL 3
CLKIN CLKIN
Transmitter Receiver
Transmitter Receiver
Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (2)
Transmitter Receiver
Transmitter Receiver
FPLL8CLK
Fast PLL 8
Up to 20 Receiver and 20 Transmitter Channels in 20 Rows (2)
Fast PLL 9
FPLL9CLK
Notes to Figure 2-75:
(1) (2) (3) Wire-bond packages support up to 624 Mbps. See Table 2-38 through 2-41 for the number of channels each device supports. There is a multiplexer here to select the PLL clock source. If a PLL uses this multiplexer to clock channels outside of its bank quadrant, those clocked channels support up to 840 Mbps for "high" speed channels and 462 Mbps for "low" speed channels as labeled in the device pin-outs at www.altera.com.
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2-139 Stratix Device Handbook, Volume 1
Power Sequencing & Hot Socketing
The transmitter external clock output is transmitted on a data channel. The txclk pin for each bank is located in between data transmitter pins. For x1 clocks (e.g., 622 Mbps, 622 MHz), the high-speed PLL clock bypasses the SERDES to drive the output pins. For half-rate clocks (e.g., 622 Mbps, 311 MHz) or any other even-numbered factor such as 1/4, 1/7, 1/8, or 1/10, the SERDES automatically generates the clock in the Quartus II software. For systems that require more than four or eight high-speed differential I/O clock domains, a SERDES bypass implementation is possible using IOEs.
Byte Alignment
For high-speed source synchronous interfaces such as POS-PHY 4, XSBI, RapidIO, and HyperTransport technology, the source synchronous clock rate is not a byte- or SERDES-rate multiple of the data rate. Byte alignment is necessary for these protocols since the source synchronous clock does not provide a byte or word boundary since the clock is one half the data rate, not one eighth. The Stratix device's high-speed differential I/O circuitry provides dedicated data realignment circuitry for usercontrolled byte boundary shifting. This simplifies designs while saving LE resources. An input signal to each fast PLL can stall deserializer parallel data outputs by one bit period. You can use an LE-based state machine to signal the shift of receiver byte boundaries until a specified pattern is detected to indicate byte alignment.
Power Sequencing & Hot Socketing
Because Stratix devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. Therefore, the VCCIO and VCCINT power supplies may be powered in any order. Although you can power up or down the VCCIO and VCCINT power supplies in any sequence, you should not power down any I/O banks that contain configuration pins while leaving other I/O banks powered on. For power up and power down, all supplies (VCCINT and all VCCIO power planes) must be powered up and down within 100 ms of each other. This prevents I/O pins from driving out. Signals can be driven into Stratix devices before and during power up without damaging the device. In addition, Stratix devices do not drive out during power up. Once operating conditions are reached and the device is configured, Stratix devices operate as specified by the user. For more information, see Hot Socketing in the Selectable I/O Standards in Stratix & Stratix GX Devices chapter in the Stratix Device Handbook, Volume 2.
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3. Configuration & Testing
S51003-1.3
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
All Stratix(R) devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be performed either before or after, but not during configuration. Stratix devices can also use the JTAG port for configuration together with either the Quartus(R) II software or hardware using either Jam Files (.jam) or Jam Byte-Code Files (.jbc). Stratix devices support IOE I/O standard setting reconfiguration through the JTAG BST chain. The JTAG chain can update the I/O standard for all input and output pins any time before or during user mode through the CONFIG_IO instruction. You can use this ability for JTAG testing before configuration when some of the Stratix pins drive or receive from other devices on the board using voltage-referenced standards. Since the Stratix device may not be configured before JTAG testing, the I/O pins may not be configured for appropriate electrical standards for chip-to-chip communication. Programming those I/O standards via JTAG allows you to fully test the I/O connection to other devices. The enhanced PLL reconfiguration bits are part of the JTAG chain before configuration and after power-up. After device configuration, the PLL reconfiguration bits are not part of the JTAG chain. The JTAG pins support 1.5-V/1.8-V or 2.5-V/3.3-V I/O standards. The TDO pin voltage is determined by the VCCIO of the bank where it resides. The VCCSEL pin selects whether the JTAG inputs are 1.5-V, 1.8-V, 2.5-V, or 3.3-V compatible. Stratix devices also use the JTAG port to monitor the logic operation of the device with the SignalTap(R) II embedded logic analyzer. Stratix devices support the JTAG instructions shown in Table 3-1. The Quartus II software has an Auto Usercode feature where you can choose to use the checksum value of a programming file as the JTAG user code. If selected, the checksum is automatically loaded to the USERCODE register. In the Settings dialog box in the Assignments menu, click Device & Pin Options, then General, and then turn on the Auto Usercode option.
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3-1
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Table 3-1. Stratix JTAG Instructions JTAG Instruction Instruction Code Description
Allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. Also used by the SignalTap II embedded logic analyzer. Allows the external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation. Selects the 32-bit USERCODE register and places it between the TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO. Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins. Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding I/O pins to a state defined by the data in the boundary-scan register. Used when configuring an Stratix device via the JTAG port with a MasterBlasterTM, ByteBlasterMVTM, or ByteBlasterTM II download cable, or when using a Jam File or Jam Byte-Code File via an embedded processor or JRunner. 00 0000 0001 00 0000 1101 Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected. Allows configuration of I/O standards through the JTAG chain for JTAG testing. Can be executed before, after, or during configuration. Stops configuration if executed during configuration. Once issued, the CONFIG_IO instruction will hold nSTATUS low to reset the configuration device. nSTATUS is held low until the device is reconfigured. Monitors internal device operation with the SignalTap II embedded logic analyzer.
SAMPLE/PRELOAD 00 0000 0101
EXTEST (1)
00 0000 0000
BYPASS
11 1111 1111
USERCODE
00 0000 0111
IDCODE
00 0000 0110 00 0000 1011
HIGHZ (1)
CLAMP (1)
00 0000 1010
ICR instructions
PULSE_NCONFIG CONFIG_IO
SignalTap II instructions Note to Table 3-1:
(1)
Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
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Configuration & Testing
The Stratix device instruction register length is 10 bits and the USERCODE register length is 32 bits. Tables 3-2 and 3-3 show the boundary-scan register length and device IDCODE information for Stratix devices.
Table 3-2. Stratix Boundary-Scan Register Length Device
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
Boundary-Scan Register Length
1,317 1,797 2,157 2,253 2,529 3,129 3,777
Table 3-3. 32-Bit Stratix Device IDCODE IDCODE (32 Bits) (1) Device Version (4 Bits)
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
(1) (2)
Part Number (16 Bits)
0010 0000 0000 0001 0010 0000 0000 0010 0010 0000 0000 0011 0010 0000 0000 0100 0010 0000 0000 0101 0010 0000 0000 0110 0010 0000 0000 0111
Manufacturer Identity (11 Bits)
000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110 000 0110 1110
LSB (1 Bit) (2)
1 1 1 1 1 1 1
0000 0000 0000 0000 0000 0000 0000
Notes to Tables 3-2 and 3-3:
The most significant bit (MSB) is on the left. The IDCODE's least significant bit (LSB) is always 1.
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3-3 Stratix Device Handbook, Volume 1
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
Figure 3-1 shows the timing requirements for the JTAG signals. Figure 3-1. Stratix JTAG Waveforms
TMS
TDI t JCP t JCH TCK tJPZX TDO tJSSU Signal to Be Captured Signal to Be Driven tJSH t JPCO t JPXZ t JCL t JPSU t JPH
tJSZX
tJSCO
tJSXZ
Table 3-4 shows the JTAG timing parameters and values for Stratix devices.
Table 3-4. Stratix JTAG Timing Parameters & Values Symbol
tJCP tJCH tJCL tJPSU tJPH tJPCO tJPZX tJPXZ tJSSU tJSH tJSCO tJSZX tJSXZ
Parameter
TCK clock period TCK clock high time TCK clock low time
JTAG port setup time JTAG port hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Capture register setup time Capture register hold time Update register clock to output Update register high impedance to valid output Update register valid output to high impedance
Min
100 50 50 20 45
Max
Unit
ns ns ns ns ns
25 25 25 20 45 35 35 35
ns ns ns ns ns ns ns ns
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Configuration & Testing
1
Stratix, Stratix II, Cyclone(R), and Cyclone II devices must be within the first 17 devices in a JTAG chain. All of these devices have the same JTAG controller. If any of the Stratix, Stratix II, Cyclone, and Cyclone II devices are in the 18th or after they will fail configuration. This does not affect SignalTap II.
f
For more information on JTAG, see the following documents:

AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices Jam Programming & Test Language Specification
SignalTap II Embedded Logic Analyzer
Stratix devices feature the SignalTap II embedded logic analyzer, which monitors design operation over a period of time through the IEEE Std. 1149.1 (JTAG) circuitry. You can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is particularly important for advanced packages, such as FineLine BGA(R) packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured. The logic, circuitry, and interconnects in the Stratix architecture are configured with CMOS SRAM elements. Altera(R) devices are reconfigurable. Because every device is tested with a high-coverage production test program, you do not have to perform fault testing and can focus on simulation and design verification. Stratix devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers in-system programmability (ISP)-capable configuration devices that configure Stratix devices via a serial data stream. Stratix devices can be configured in under 100 ms using 8-bit parallel data at 100 MHz. The Stratix device's optimized interface allows microprocessors to configure it serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat Stratix devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy. After a Stratix device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Real-time changes can be made during system operation, enabling innovative reconfigurable computing applications.
Configuration
Operating Modes
The Stratix architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called configuration. During initialization, which occurs immediately after
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Configuration
configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. Together, the configuration and initialization processes are called command mode. Normal device operation is called user mode. SRAM configuration elements allow Stratix devices to be reconfigured incircuit by loading new configuration data into the device. With real-time reconfiguration, the device is forced into command mode with a device pin. The configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. You can perform in-field upgrades by distributing new configuration files either within the system or remotely. PORSEL is a dedicated input pin used to select POR delay times of 2 ms or 100 ms during power-up. When the PORSEL pin is connected to ground, the POR time is 100 ms; when the PORSEL pin is connected to VCC, the POR time is 2 ms. The nIO_PULLUP pin enables a built-in weak pull-up resistor to pull all user I/O pins to VCCIO before and during device configuration. If nIO_PULLUP is connected to VCC during configuration, the weak pullups on all user I/O pins are disabled. If connected to ground, the pull-ups are enabled during configuration. The nIO_PULLUP pin can be pulled to 1.5, 1.8, 2.5, or 3.3 V for a logic level high. VCCSEL is a dedicated input that is used to choose whether all dedicated configuration and JTAG input pins can accept 1.5 V/1.8 V or 2.5 V/3.3 V during configuration. A logic low sets 3.3 V/2.5 V, and a logic high sets 1.8 V/1.5 V. VCCSEL affects the following pins: TDI, TMS, TCK, TRST, MSEL0, MSEL1, MSEL2, nCONFIG, nCE, DCLK, PLL_ENA, CONF_DONE, nSTATUS. The VCCSEL pin can be pulled to 1.5, 1.8, 2.5, or 3.3 V for a logic level high. The VCCSEL signal does not control the dual-purpose configuration pins such as the DATA[7..0] and PPA pins (nWS, nRS, CS, nCS, and RDYnBSY). During configuration, these dual-purpose pins will drive out voltage levels corresponding to the VCCIO supply voltage that powers the I/O bank containing the pin. After configuration, the dual-purpose pins use I/O standards specified in the user design. TDO and nCEO drive out at the same voltages as the VCCIO supply that powers the I/O bank containing the pin. Users must select the VCCIO supply for bank containing TDO accordingly. For example, when using the ByteBlasterTM MV cable, the VCCIO for the bank containing TDO must be powered up at 3.3 V.
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Configuration & Testing
Configuring Stratix FPGAs with JRunner
JRunner is a software driver that configures Altera FPGAs, including Stratix FPGAs, through the ByteBlaster II or ByteBlasterMV cables in JTAG mode. The programming input file supported is in Raw Binary File (.rbf) format. JRunner also requires a Chain Description File (.cdf) generated by the Quartus II software. JRunner is targeted for embedded JTAG configuration. The source code is developed for the Windows NT operating system (OS), but can be customized to run on other platforms. For more information on the JRunner software driver, see the JRunner Software Driver: An Embedded Solution to the JTAG Configuration White Paper and the source files on the Altera web site (www.altera.com).
Configuration Schemes
You can load the configuration data for a Stratix device with one of five configuration schemes (see Table 3-5), chosen on the basis of the target application. You can use a configuration device, intelligent controller, or the JTAG port to configure a Stratix device. A configuration device can automatically configure a Stratix device at system power-up. Multiple Stratix devices can be configured in any of five configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device.
Table 3-5. Data Sources for Configuration Configuration Scheme
Configuration device Passive serial (PS) Passive parallel asynchronous (PPA) Fast passive parallel JTAG
Data Source
Enhanced or EPC2 configuration device MasterBlaster, ByteBlasterMV, or ByteBlaster II download cable or serial data source Parallel data source Parallel data source MasterBlaster, ByteBlasterMV, or ByteBlaster II download cable, a microprocessor with a Jam or JBC file, or JRunner
Partial Reconfiguration
The enhanced PLLs within the Stratix device family support partial reconfiguration of their multiply, divide, and time delay settings without reconfiguring the entire device. You can use either serial data from the logic array or regular I/O pins to program the PLL's counter settings in a serial chain. This option provides considerable flexibility for frequency
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Configuration
synthesis, allowing real-time variation of the PLL frequency and delay. The rest of the device is functional while reconfiguring the PLL. See the Stratix Architecture chapter of the Stratix Device Handbook, Volume 1 for more information on Stratix PLLs.
Remote Update Configuration Modes
Stratix devices also support remote configuration using an Altera enhanced configuration device (e.g., EPC16, EPC8, and EPC4 devices) with page mode selection. Factory configuration data is stored in the default page of the configuration device. This is the default configuration that contains the design required to control remote updates and handle or recover from errors. You write the factory configuration once into the flash memory or configuration device. Remote update data can update any of the remaining pages of the configuration device. If there is an error or corruption in a remote update configuration, the configuration device reverts back to the factory configuration information. There are two remote configuration modes: remote and local configuration. You can use the remote update configuration mode for all three configuration modes: serial, parallel synchronous, and parallel asynchronous. Configuration devices (for example, EPC16 devices) only support serial and parallel synchronous modes. Asynchronous parallel mode allows remote updates when an intelligent host is used to configure the Stratix device. This host must support page mode settings similar to an EPC16 device.
Remote Update Mode
When the Stratix device is first powered up in remote update programming mode, it loads the configuration located at page address "000." The factory configuration should always be located at page address "000," and should never be remotely updated. The factory configuration contains the required logic to perform the following operations:

Determine the page address/load location for the next application's configuration data Recover from a previous configuration error Receive new configuration data and write it into the configuration device
The factory configuration is the default and takes control if an error occurs while loading the application configuration.
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Configuration & Testing
While in the factory configuration, the factory-configuration logic performs the following operations:

Loads a remote update-control register to determine the page address of the new application configuration Determines whether to enable a user watchdog timer for the application configuration Determines what the watchdog timer setting should be if it is enabled
The user watchdog timer is a counter that must be continually reset within a specific amount of time in the user mode of an application configuration to ensure that valid configuration occurred during a remote update. Only valid application configurations designed for remote update can reset the user watchdog timer in user mode. If a valid application configuration does not reset the user watchdog timer in a specific amount of time, the timer updates a status register and loads the factory configuration. The user watchdog timer is automatically disabled for factory configurations. If an error occurs in loading the application configuration, the configuration logic writes a status register to specify the cause of the error. Once this occurs, the Stratix device automatically loads the factory configuration, which reads the status register and determines the reason for reconfiguration. Based on the reason, the factory configuration will take appropriate steps and will write the remote update control register to specify the next application configuration page to be loaded. When the Stratix device successfully loads the application configuration, it enters into user mode. The Stratix device then executes the main application of the user. Intellectual property (IP), such as a Nios(R) (16-bit ISA) and Nios(R) II (32-bit ISA) embedded processors, can help the Stratix device determine when remote update is coming. The Nios embedded processor or user logic receives incoming data, writes it to the configuration device, and loads the factory configuration. The factory configuration will read the remote update status register and determine the valid application configuration to load. Figure 3-2 shows the Stratix remote update. Figure 3-3 shows the transition diagram for remote update mode.
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Configuration
Figure 3-2. Stratix Device Remote Update
(1)
Configuration Device
Watchdog Timer New Remote Configuration Data
Application Configuration Application Configuration
Page 7 Page 6
Stratix Device Factory Configuration Configuration Device Updates Stratix Device with Factory Configuration (to Handle Update) or New Application Configuration
Page 0
Note to Figure 3-2:
(1) When the Stratix device is configured with the factory configuration, it can handle update data from EPC16, EPC8, or EPC4 configuration device pages and point to the next page in the configuration device.
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Configuration & Testing
Figure 3-3. Remote Update Transition Diagram Notes (1), (2)
Power-Up
Application 1 Configuration
Configuration Error
Configuration Error
Reload an Application
Factory Configuration
Reload an Application
Configuration Error
Application n Configuration
Notes to Figure 3-3:
(1) (2) Remote update of Application Configuration is controlled by a Nios embedded processor or user logic programmed in the Factory or Application configurations. Up to seven pages can be specified allowing up to seven different configuration applications.
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Stratix Automated Single Event Upset (SEU) Detection
Local Update Mode
Local update mode is a simplified version of the remote update. This feature is intended for simple systems that need to load a single application configuration immediately upon power up without loading the factory configuration first. Local update designs have only one application configuration to load, so it does not require a factory configuration to determine which application configuration to use. Figure 3-4 shows the transition diagram for local update mode. Figure 3-4. Local Update Transition Diagram
Power-Up or nCONFIG
nCONFIG
Application Configuration
Configuration Error
Configuration Error
nCONFIG
Factory Configuration
Stratix Automated Single Event Upset (SEU) Detection
Stratix devices offer on-chip circuitry for automated checking of single event upset (SEU) detection. FPGA devices that operate at high elevations or in close proximity to earth's North or South Pole require periodic checks to ensure continued data integrity. The error detection cyclic redundancy check (CRC) feature controlled by the Device & Pin Options dialog box in the Quartus II software uses a 32-bit CRC circuit to ensure data reliability and is one of the best options for mitigating SEU.
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Configuration & Testing
For Stratix, the CRC is computed by the Quartus II software and downloaded into the device as a part of the configuration bit stream. The CRC_ERROR pin reports a soft error when configuration SRAM data is corrupted, triggering device reconfiguration.
Custom-Built Circuitry
Dedicated circuitry is built in the Stratix devices to perform error detection automatically. You can use the built-in dedicated circuitry for error detection using CRC feature in Stratix devices, eliminating the need for external logic. This circuitry will perform error detection automatically when enabled. This error detection circuitry in Stratix devices constantly checks for errors in the configuration SRAM cells while the device is in user mode. You can monitor one external pin for the error and use it to trigger a re-configuration cycle. Select the desired time between checks by adjusting a built-in clock divider.
Software Interface
In the Quartus II software version 4.1 and later, you can turn on the automated error detection CRC feature in the Device & Pin Options dialog box. This dialog box allows you to enable the feature and set the internal frequency of the CRC between 400 kHz to 100 MHz. This controls the rate that the CRC circuitry verifies the internal configuration SRAM bits in the FPGA device. For more information on CRC, see AN 357: Error Detection Using CRC in Altera FPGA Devices.
Temperature Sensing Diode
Stratix devices include a diode-connected transistor for use as a temperature sensor in power management. This diode is used with an external digital thermometer device such as a MAX1617A or MAX1619 from MAXIM Integrated Products. These devices steer bias current through the Stratix diode, measuring forward voltage and converting this reading to temperature in the form of an 8-bit signed number (7 bits plus sign). The external device's output represents the junction temperature of the Stratix device and can be used for intelligent power management. The diode requires two pins (tempdiodep and tempdioden) on the Stratix device to connect to the external temperature-sensing device, as shown in Figure 3-5. The temperature sensing diode is a passive element and therefore can be used before the Stratix device is powered.
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Temperature Sensing Diode
Figure 3-5. External Temperature-Sensing Diode
Stratix Device Temperature-Sensing Device
tempdiodep
tempdioden
Table 3-6 shows the specifications for bias voltage and current of the Stratix temperature sensing diode.
Table 3-6. Temperature-Sensing Diode Electrical Characteristics Parameter
IBIAS high IBIAS low VBP - VBN VBN Series resistance
Minimum
80 8 0.3
Typical
100 10
Maximum
120 12 0.9
Unit
A A V V
0.7 3
W
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Configuration & Testing
The temperature-sensing diode works for the entire operating range shown in Figure 3-6. Figure 3-6. Temperature vs. Temperature-Sensing Diode Voltage
0.95 0.90 0.85 0.80 0.75 Voltage (Across Diode) 0.70 0.65 0.60 0.55 0.50 0.45 0.40 -55 -30 -5 20 45 70 95 120 100 A Bias Current 10 A Bias Current
Temperature ( C)
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Temperature Sensing Diode
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4. DC & Switching Characteristics
S51004-3.3
Operating Conditions
Stratix(R) devices are offered in both commercial and industrial grades. Industrial devices are offered in -6 and -7 speed grades and commercial devices are offered in -5 (fastest), -6, -7, and -8 speed grades. This section specifies the operation conditions for operating junction temperature, VCCINT and VCCIO voltage levels, and input voltage requirements. The voltage specifications in this section are specified at the pins of the device (and not the power supply). If the device operates outside these ranges, then all DC and AC specifications are not guaranteed. Furthermore, the reliability of the device may be affected. The timing parameters in this chapter apply to both commercial and industrial temperature ranges unless otherwise stated. Tables 4-1 through 4-8 provide information on absolute maximum ratings.
Table 4-1. Stratix Device Absolute Maximum Ratings Notes (1), (2) Symbol
VCCINT VCCIO VI IOUT TSTG TJ DC input voltage (3) DC output current, per pin Storage temperature Junction temperature No bias BGA packages under bias
Parameter
Supply voltage
Conditions
With respect to ground
Minimum
-0.5 -0.5 -0.5 -25 -65
Maximum
2.4 4.6 4.6 40 150 135
Unit
V V V mA C C
Table 4-2. Stratix Device Recommended Operating Conditions (Part 1 of 2) Symbol
VCCINT
Parameter
Supply voltage for internal logic and input buffers (4)
Conditions
Minimum
1.425
Maximum
1.575
Unit
V
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4-1
Operating Conditions
Table 4-2. Stratix Device Recommended Operating Conditions (Part 2 of 2) Symbol
VCCIO
Parameter
Supply voltage for output buffers, 3.3-V operation Supply voltage for output buffers, 2.5-V operation Supply voltage for output buffers, 1.8-V operation Supply voltage for output buffers, 1.5-V operation
Conditions
(4), (5) (4) (4) (4) (3), (6)
Minimum
3.00 (3.135) 2.375 1.71 1.4 -0.5 0
Maximum
3.60 (3.465) 2.625 1.89 1.6 4.0 VCCIO 85 100
Unit
V V V V V V C C
VI VO TJ
Input voltage Output voltage Operating junction temperature
For commercial use For industrial use
0 -40
Table 4-3. Stratix Device DC Operating Conditions Note (7) (Part 1 of 2) Symbol
II IOZ ICC0
Parameter
Input pin leakage current Tri-stated I/O pin leakage current VCC supply current (standby) (All memory blocks in power-down mode)
Conditions
VI = VCCIOmax to 0 V (8) VO = VCCIOmax to 0 V (8) VI = ground, no load, no toggling inputs EP1S10. VI = ground, no load, no toggling inputs EP1S20. VI = ground, no load, no toggling inputs EP1S25. VI = ground, no load, no toggling inputs EP1S30. VI = ground, no load, no toggling inputs EP1S40. VI = ground, no load, no toggling inputs EP1S60. VI = ground, no load, no toggling inputs EP1S80. VI = ground, no load, no toggling inputs
Minimum
-10 -10
Typical
Maximum
10 10
Unit
A A mA
37 65 90 114 145 200 277
mA mA mA mA mA mA mA
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DC & Switching Characteristics
Table 4-3. Stratix Device DC Operating Conditions Note (7) (Part 2 of 2) Symbol
RCONF
Parameter
Conditions
Minimum
20 30 60
Typical
Maximum
50 80 150
Unit
k k k
Value of I/O pin pull- VCCIO = 3.0 V (9) up resistor before VCCIO = 2.375 V (9) and during VCCIO = 1.71 V (9) configuration
Table 4-4. LVTTL Specifications Symbol
VCCIO VI H VIL VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0 1.7 -0.5
Maximum
3.6 4.1 0.7
Unit
V V V V
IOH = -4 to -24 mA (10) IOL = 4 to 24 mA (10)
2.4 0.45
V
Table 4-5. LVCMOS Specifications Symbol
VCCIO VIH VIL VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0 1.7 -0.5
Maximum
3.6 4.1 0.7
Unit
V V V V
VCCIO = 3.0, IOH = -0.1 mA VCCIO = 3.0, IOL = 0.1 mA
VCCIO - 0.2 0.2
V
Table 4-6. 2.5-V I/O Specifications Symbol
VCCIO VIH VIL VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 1.7 -0.5
Maximum
2.625 4.1 0.7
Unit
V V V V
IOH = -1 mA (10) IOL = 1 mA (10)
2.0 0.4
V
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Operating Conditions
Table 4-7. 1.8-V I/O Specifications Symbol
VCCIO VI H VIL VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.65 0.65 x VCCIO -0.3
Maximum
1.95 2.25 0.35 x VCCIO
Unit
V V V V
IOH = -2 to -8 mA (10) IOL = 2 to 8 mA (10)
VCCIO - 0.45 0.45
V
Table 4-8. 1.5-V I/O Specifications Symbol
VCCIO VI H VIL VOH VOL
(1) (2)
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.4 0.65 x VCCIO -0.3 0.75 x VCCIO
Maximum
1.6 VCCIO + 0.3 0.35 x VCCIO 0.25 x VCCIO
Unit
V V V V V
IOH = -2 mA (10) IOL = 2 mA (10)
Notes to Tables 4-1 through 4-8:
See the Operating Requirements for Altera Devices Data Sheet. Conditions beyond those listed in Table 4-1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device. (3) Minimum DC input is -0.5 V. During transitions, the inputs may undershoot to -2.0 V for input currents less than 100 mA and periods shorter than 20 ns, or overshoot to the voltage shown in Table 4-9, based on input duty cycle for input currents less than 100 mA. The overshoot is dependent upon duty cycle of the signal. The DC case is equivalent to 100% duty cycle. (4) Maximum VCC rise time is 100 ms, and VCC must rise monotonically. (5) VCCIO maximum and minimum conditions for LVPECL, LVDS, and 3.3-V PCML are shown in parentheses. (6) All pins, including dedicated inputs, clock, I/O, and JTAG pins, may be driven before VCCINT and VCCIO are powered. (7) Typical values are for TA = 25C, VCCINT = 1.5 V, and VCCIO = 1.5 V, 1.8 V, 2.5 V, and 3.3 V. (8) This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO settings (3.3, 2.5, 1.8, and 1.5 V). (9) Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO. (10) Drive strength is programmable according to the values shown in the Stratix Architecture chapter of the Stratix Device Handbook, Volume 1.
Table 4-9. Overshoot Input Voltage with Respect to Duty Cycle (Part 1 of 2) Vin (V)
4.0 4.1 4.2
Maximum Duty Cycle (%)
100 90 50
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DC & Switching Characteristics
Table 4-9. Overshoot Input Voltage with Respect to Duty Cycle (Part 2 of 2) Vin (V)
4.3 4.4 4.5
Maximum Duty Cycle (%)
30 17 10
Figures 4-1 and 4-2 show receiver input and transmitter output waveforms, respectively, for all differential I/O standards (LVDS, 3.3-V PCML, LVPECL, and HyperTransport technology). Figure 4-1. Receiver Input Waveforms for Differential I/O Standards
Single-Ended Waveform Positive Channel (p) = VIH VID Negative Channel (n) = VIL VCM Ground
Differential Waveform
VID p-n=0V VID
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Operating Conditions
Figure 4-2. Transmitter Output Waveforms for Differential I/O Standards
Single-Ended Waveform Positive Channel (p) = VOH VOD Negative Channel (n) = VOL VCM Ground
Differential Waveform
VOD p-n=0V VOD
Tables 4-10 through 4-33 recommend operating conditions, DC operating conditions, and capacitance for 1.5-V Stratix devices.
Table 4-10. 3.3-V LVDS I/O Specifications (Part 1 of 2) Symbol
VCCIO VID (6)
Parameter
I/O supply voltage Input differential voltage swing (single-ended)
Conditions
0.1 V VCM < 1.1 V W = 1 through 10 1.1 V VCM 1.6 V W=1 1.1 V VCM 1.6 V W = 2 through10 1.6 V < VCM 1.8 V W = 1 through 10
Minimum
3.135 300 200 100 300
Typical
3.3
Maximum
3.465 1,000 1,000 1,000 1,000
Unit
V mV mV mV mV
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DC & Switching Characteristics
Table 4-10. 3.3-V LVDS I/O Specifications (Part 2 of 2) Symbol
VICM
Parameter
Input common mode voltage (6)
Conditions
LVDS 0.3 V VID 1.0 V W = 1 through 10 LVDS 0.3 V VID 1.0 V W = 1 through 10 LVDS 0.2 V VID 1.0 V W=1 LVDS 0.1 V VID 1.0 V W = 2 through 10
Minimum
100
Typical
Maximum
1,100
Unit
mV
1,600
1,800
mV
1,100
1,600
mV
1,100
1,600
mV
VOD (1) VOD VOCM VOCM RL
Output differential voltage (single-ended) Change in VOD between high and low Output common mode voltage Change in VOCM between high and low Receiver differential input discrete resistor (external to Stratix devices)
RL = 100 RL = 100 RL = 100 RL = 100
250
375
550 50
mV mV mV mV
1,125
1,200
1,375 50
90
100
110
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Operating Conditions
Table 4-11. 3.3-V PCML Specifications Symbol
VCCIO VID (peakto-peak) VICM VOD VOD VOCM VOCM VT R1 R2
Parameter
I/O supply voltage Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Change in VOD between high and low Output common mode voltage Change in VOCM between high and low Output termination voltage Output external pull-up resistors Output external pull-up resistors
Conditions
Minimum
3.135 300 1.5 300
Typical
3.3
Maximum
3.465 600 3.465
Unit
V mV V mV mV V mV V
370
500 50
2.5
2.85
3.3 50
VCCIO 45 45 50 50 55 55

Table 4-12. LVPECL Specifications Symbol
VCCIO VID (peakto-peak) VICM VOD VOCM RL
Parameter
I/O supply voltage Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Output common mode voltage Receiver differential input resistor
Conditions
Minimum
3.135 300 1
Typical
3.3
Maximum
3.465 1,000 2
Unit
V mV V mV V
RL = 100 RL = 100
525 1.5 90
700 1.7 100
970 1.9 110
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DC & Switching Characteristics
Table 4-13. HyperTransport Technology Specifications Symbol
VCCIO VID (peakto-peak) VICM VOD VOD VOCM VOCM RL
Parameter
I/O supply voltage Input differential voltage swing (single-ended) Input common mode voltage Output differential voltage (single-ended) Change in VOD between high and low Output common mode voltage Change in VOCM between high and low Receiver differential input resistor
Conditions
Minimum
2.375 300 300
Typical
2.5
Maximum
2.625 900 900
Unit
V mV mV mV mV mV mV
RL = 100 RL = 100 RL = 100 RL = 100
380
485
820 50
440
650
780 50
90
100
110
Table 4-14. 3.3-V PCI Specifications Symbol
VCCIO VIH VIL VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0 0.5 x VCCIO -0.5
Typical
3.3
Maximum
3.6 VCCIO + 0.5 0.3 x VCCIO
Unit
V V V V
IOUT = -500 A IOUT = 1,500 A
0.9 x VCCIO 0.1 x VCCIO
V
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Operating Conditions
Table 4-15. PCI-X 1.0 Specifications Symbol
VCCIO VIH VIL VIPU VOH VOL
Parameter
Output supply voltage High-level input voltage Low-level input voltage Input pull-up voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0 0.5 x VCCIO -0.5 0.7 x VCCIO
Typical
Maximum
3.6 VCCIO + 0.5 0.35 x VCCIO
Unit
V V V V V
IOUT = -500 A IOUT = 1,500 A
0.9 x VCCIO 0.1 x VCCIO
V
Table 4-16. GTL+ I/O Specifications Symbol
VTT VREF VIH VIL VOL
Parameter
Termination voltage Reference voltage High-level input voltage Low-level input voltage Low-level output voltage
Conditions
Minimum
1.35 0.88 VREF + 0.1
Typical
1.5 1.0
Maximum
1.65 1.12
Unit
V V V
VREF - 0.1 IOL = 34 mA (3) 0.65
V V
Table 4-17. GTL I/O Specifications Symbol
VTT VREF VIH VIL VOL
Parameter
Termination voltage Reference voltage High-level input voltage Low-level input voltage Low-level output voltage
Conditions
Minimum
1.14 0.74 VREF + 0.05
Typical
1.2 0.8
Maximum
1.26 0.86
Unit
V V V
VREF - 0.05 IOL = 40 mA (3) 0.4
V V
4-10 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-18. SSTL-18 Class I Specifications Symbol
VCCIO VREF VTT VIH(DC) VIL(DC) VIH(AC) VIL(AC) VOH VOL
Parameter
Output supply voltage Reference voltage Termination voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.65 0.8 VREF - 0.04 VREF + 0.125
Typical
1.8 0.9 VREF
Maximum
1.95 1.0 VREF + 0.04
Unit
V V V V
VREF - 0.125 VREF + 0.275 VREF - 0.275 IOH = -6.7 mA (3) IOL = 6.7 mA (3) VTT + 0.475 VTT - 0.475
V V V V V
Table 4-19. SSTL-18 Class II Specifications Symbol
VCCIO VREF VTT VIH(DC) VIL(DC) VIH(AC) VIL(AC) VOH VOL
Parameter
Output supply voltage Reference voltage Termination voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.65 0.8 VREF - 0.04 VREF + 0.125
Typical
1.8 0.9 VREF
Maximum
1.95 1.0 VREF + 0.04
Unit
V V V V
VREF - 0.125 VREF + 0.275 VREF - 0.275 IOH = -13.4 mA (3) IOL = 13.4 mA (3) VTT + 0.630 VTT - 0.630
V V V V V
Altera Corporation July 2005
4-11 Stratix Device Handbook, Volume 1
Operating Conditions
Table 4-20. SSTL-2 Class I Specifications Symbol
VCCIO VTT VREF VIH(DC) VIL(DC) VIH(AC) VIL(AC) VOH VOL
Parameter
Output supply voltage Termination voltage Reference voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 VREF - 0.04 1.15 VREF + 0.18 -0.3 VREF + 0.35
Typical
2.5 VREF 1.25
Maximum
2.625 VREF + 0.04 1.35 3.0 VREF - 0.18
Unit
V V V V V V
VREF - 0.35 IOH = -8.1 mA (3) IOL = 8.1 mA (3) VTT + 0.57 VTT - 0.57
V V V
Table 4-21. SSTL-2 Class II Specifications Symbol
VCCIO VTT VREF VIH(DC) VIL(DC) VIH(AC) VIL(AC) VOH VOL
Parameter
Output supply voltage Termination voltage Reference voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
2.375 VREF - 0.04 1.15 VREF + 0.18 -0.3 VREF + 0.35
Typical
2.5 VREF 1.25
Maximum
2.625 VREF + 0.04 1.35 VCCIO + 0.3 VREF - 0.18
Unit
V V V V V V
VREF - 0.35 IOH = -16.4 mA (3) IOL = 16.4 mA (3) VTT + 0.76 VTT - 0.76
V V V
Table 4-22. SSTL-3 Class I Specifications (Part 1 of 2) Symbol
VCCIO VTT VREF VIH(DC) VIL(DC) VIH(AC)
Parameter
Output supply voltage Termination voltage Reference voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage
Conditions
Minimum
3.0 VREF - 0.05 1.3 VREF + 0.2 -0.3 VREF + 0.4
Typical
3.3 VREF 1.5
Maximum
3.6 VREF + 0.05 1.7 VCCIO + 0.3 VREF - 0.2
Unit
V V V V V V
4-12 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-22. SSTL-3 Class I Specifications (Part 2 of 2) Symbol
VIL(AC) VOH VOL
Parameter
Low-level AC input voltage High-level output voltage Low-level output voltage
Conditions
IOH = -8 mA (3) IOL = 8 mA (3)
Minimum
Typical
Maximum
VREF - 0.4
Unit
V V
VTT + 0.6 VTT - 0.6
V
Table 4-23. SSTL-3 Class II Specifications Symbol
VCCIO VTT VREF VIH(DC) VIL(DC) VIH(AC) VIL(AC) VOH VOL
Parameter
Output supply voltage Termination voltage Reference voltage High-level DC input voltage Low-level DC input voltage High-level AC input voltage Low-level AC input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
3.0 VREF - 0.05 1.3 VREF + 0.2 -0.3 VREF + 0.4
Typical
3.3 VREF 1.5
Maximum
3.6 VREF + 0.05 1.7 VCCIO + 0.3 VREF - 0.2
Unit
V V V V V V
VREF - 0.4 IOH = -16 mA (3) IOL = 16 mA (3) VT T + 0.8 VTT - 0.8
V V V
Table 4-24. 3.3-V AGP 2x Specifications Symbol
VCCIO VREF VIH VIL VOH VOL
Parameter
Output supply voltage Reference voltage High-level input voltage (4) Low-level input voltage (4) High-level output voltage Low-level output voltage
Conditions
Minimum
3.15 0.39 x VCCIO 0.5 x VCCIO 0.9 x VCCIO
Typical
3.3
Maximum
3.45 0.41 x VCCIO VCCIO + 0.5 0.3 x VCCIO
Unit
V V V V V V
IOUT = -0.5 mA IOUT = 1.5 mA
3.6 0.1 x VCCIO
Table 4-25. 3.3-V AGP 1x Specifications (Part 1 of 2) Symbol
VCCIO VIH VIL
Parameter
Output supply voltage High-level input voltage (4) Low-level input voltage (4)
Conditions
Minimum
3.15 0.5 x VCCIO
Typical
3.3
Maximum
3.45 VCCIO + 0.5 0.3 x VCCIO
Unit
V V V
Altera Corporation July 2005
4-13 Stratix Device Handbook, Volume 1
Operating Conditions
Table 4-25. 3.3-V AGP 1x Specifications (Part 2 of 2) Symbol
VOH VOL
Parameter
High-level output voltage Low-level output voltage
Conditions
IOUT = -0.5 mA IOUT = 1.5 mA
Minimum
0.9 x VCCIO
Typical
Maximum
3.6 0.1 x VCCIO
Unit
V V
Table 4-26. 1.5-V HSTL Class I Specifications Symbol
VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
Parameter
Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.4 0.68 0.7 VREF + 0.1 -0.3 VREF + 0.2
Typical
1.5 0.75 0.75
Maximum
1.6 0.9 0.8
Unit
V V V V
VREF - 0.1
V V
VREF - 0.2 IOH = -8 mA (3) IOL = 8 mA (3) VCCIO - 0.4 0.4
V V V
Table 4-27. 1.5-V HSTL Class II Specifications Symbol
VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
Parameter
Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.4 0.68 0.7 VREF + 0.1 -0.3 VREF + 0.2
Typical
1.5 0.75 0.75
Maximum
1.6 0.9 0.8
Unit
V V V V
VREF - 0.1
V V
VREF - 0.2 IOH = -16 mA (3) IOL = 16 mA (3) VCCIO - 0.4 0.4
V V V
4-14 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-28. 1.8-V HSTL Class I Specifications Symbol
VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
Parameter
Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.65 0.70
Typical
1.80 0.90 VCCIO x 0.5
Maximum
1.95 0.95
Unit
V V V V
VREF + 0.1 -0.5 VREF + 0.2 VREF - 0.2 IOH = -8 mA (3) IOL = 8 mA (3) VCCIO - 0.4 0.4 VREF - 0.1
V V V V V
Table 4-29. 1.8-V HSTL Class II Specifications Symbol
VCCIO VREF VTT VIH (DC) VIL (DC) VIH (AC) VIL (AC) VOH VOL
Parameter
Output supply voltage Input reference voltage Termination voltage DC high-level input voltage DC low-level input voltage AC high-level input voltage AC low-level input voltage High-level output voltage Low-level output voltage
Conditions
Minimum
1.65 0.70
Typical
1.80 0.90 VCCIO x 0.5
Maximum
1.95 0.95
Unit
V V V V
VREF + 0.1 -0.5 VREF + 0.2 VREF - 0.2 IOH = -16 mA (3) IOL = 16 mA (3) VCCIO - 0.4 0.4 VREF - 0.1
V V V V V
Table 4-30. 1.5-V Differential HSTL Class I & Class II Specifications Symbol
VCCIO VDIF (DC) VCM (DC) VDIF (AC)
Parameter
I/O supply voltage DC input differential voltage DC common mode input voltage AC differential input voltage
Conditions
Minimum
1.4 0.2 0.68 0.4
Typical
1.5
Maximum
1.6
Unit
V V
0.9
V V
Altera Corporation July 2005
4-15 Stratix Device Handbook, Volume 1
Operating Conditions
Table 4-31. CTT I/O Specifications Symbol
VCCIO VTT/VREF VIH VIL VOH VOL IO
Parameter
Output supply voltage Termination and input reference voltage High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Output leakage current (when output is high Z)
Conditions
Minimum
2.05 1.35 VREF + 0.2
Typical
3.3 1.5
Maximum
3.6 1.65
Unit
V V V
VREF - 0.2 IOH = -8 mA IOL = 8 mA GND VOUT VCCIO -10 VREF + 0.4 VREF - 0.4 10
V V V A
Table 4-32. Bus Hold Parameters VCCIO Level Parameter Conditions 1.5 V Min
Low sustaining current VIN > VIL (maximum) 25 -25 160 -160 0.5 1.0 0.68
1.8 V Min
30 -30 200 -200 1.07 0.7
2.5 V Min
50 -50 300 -300 1.7 0.8
3.3 V Min
70 -70 500 -500 2.0
Unit
Max
Max
Max
Max
A A A A V
High sustaining VIN < VIH current (minimum) Low overdrive current High overdrive current Bus-hold trip point 0 V < VIN < VCCIO 0 V < VIN < VCCIO
4-16 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-33. Stratix Device Capacitance Note (5) Symbol
CIOTB CIOLR
Parameter
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8. Input capacitance on I/O pins in I/O banks 1, 2, 5, and 6, including high-speed differential receiver and transmitter pins. Input capacitance on top/bottom clock input pins: CLK[4:7] and CLK[12:15]. Input capacitance on left/right clock inputs:
Minimum
Typical
11.5 8.2
Maximum
Unit
pF pF
CCLKTB CCLKLR CCLKLR+
11.5 7.8 4.4
pF pF pF
CLK1, CLK3, CLK8, CLK10.
Input capacitance on left/right clock inputs: CLK0, CLK2, CLK9, and CLK11.
Notes to Tables 4-10 through 4-33:
(1) (2) (3) (4) (5) (6) When tx_outclock port of altlvds_tx megafunction is 717 MHz, VO D ( m i n ) = 235 mV on the output clock pin. Pin pull-up resistance values will lower if an external source drives the pin higher than VCCIO. Drive strength is programmable according to the values shown in the Stratix Architecture chapter of the Stratix Device Handbook, Volume 1. VREF specifies the center point of the switching range. Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within 0.5 pF. VIO and VCM have multiple ranges and values for J=1 through 10.
Power Consumption
Altera(R) offers two ways to calculate power for a design: the Altera web power calculator and the PowerGaugeTM feature in the Quartus(R) II software. The interactive power calculator on the Altera web site is typically used prior to designing the FPGA in order to get a magnitude estimate of the device power. The Quartus II software PowerGauge feature allows you to apply test vectors against your design for more accurate power consumption modeling. In both cases, these calculations should only be used as an estimation of power, not as a specification. Stratix devices require a certain amount of power-up current to successfully power up because of the small process geometry on which they are fabricated. Table 4-34 shows the maximum power-up current (ICCINT) required to power a Stratix device. This specification is for commercial operating conditions. Measurements were performed with an isolated Stratix device on the board to characterize the power-up current of an isolated
Altera Corporation July 2005
4-17 Stratix Device Handbook, Volume 1
Power Consumption
device. Decoupling capacitors were not used in this measurement. To factor in the current for decoupling capacitors, sum up the current for each capacitor using the following equation: I = C (dV/dt) If the regulator or power supply minimum output current is more than the Stratix device requires, then the device may consume more current than the maximum current listed in Table 4-34. However, the device does not require any more current to successfully power up than what is listed in Table 4-34.
Table 4-34. Stratix Power-Up Current (ICCINT) Requirements Note (1) Power-Up Current Requirement Device Typical
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 Note to Table 4-34:
(1) The maximum test conditions are for 0 C and typical test conditions are for 40 C.
Unit Maximum
700 1,200 1,500 1,900 2,300 2,600 3,000 mA mA mA mA mA mA mA 250 400 500 550 650 800 1,000
The exact amount of current consumed varies according to the process, temperature, and power ramp rate. Stratix devices typically require less current during power up than shown in Table 4-34. The user-mode current during device operation is generally higher than the power-up current. The duration of the ICCINT power-up requirement depends on the VCCINT voltage supply rise time. The power-up current consumption drops when the VCCINT supply reaches approximately 0.75 V.
4-18 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Timing Model
The DirectDriveTM technology and MultiTrackTM interconnect ensure predictable performance, accurate simulation, and accurate timing analysis across all Stratix device densities and speed grades. This section describes and specifies the performance, internal, external, and PLL timing specifications. All specifications are representative of worst-case supply voltage and junction temperature conditions.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The Quartus II software issues an informational message during the design compilation if the timing models are preliminary. Table 4-35 shows the status of the Stratix device timing models. Preliminary status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible. Final timing numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under worstcase voltage and junction temperature conditions.
Table 4-35. Stratix Device Timing Model Status Device
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
Preliminary
Final v v v v v v v
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4-19 Stratix Device Handbook, Volume 1
Timing Model
Performance
Table 4-36 shows Stratix performance for some common designs. All performance values were obtained with Quartus II software compilation of LPM, or MegaCore(R) functions for the FIR and FFT designs.
Table 4-36. Stratix Performance (Part 1 of 2) Notes (1), (2) Resources Used Applications TriMatrix DSP LEs Memory Blocks Blocks
22 46 16 64 0 30 0 0 34 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
Performance -5 Speed Grade
407.83 318.26 422.11 321.85 317.76 319.18 290.86 290.86 290.86 255.95 255.95 255.95
-6 Speed Grade
324.56 255.29 422.11 290.52 277.62 278.86 255.55 255.55 255.55 223.06 233.06 233.06
-7 Speed Grade
288.68 242.89 390.01 261.23 241.48 242.54 222.27 222.27 222.27 194.06 194.06 194.06
-8 Speed Grade
228.67 185.18 348.67 220.5 205.21 206.14 188.89 188.89 188.89 164.93 164.93 164.93
Units
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
LE
16-to-1 multiplexer (1) 32-to-1 multiplexer (3) 16-bit counter 64-bit counter
Simple dual-port RAM TriMatrix 32 x 18 bit memory M512 block FIFO 32 x 18 bit TriMatrix memory M4K block Simple dual-port RAM 128 x 36 bit True dual-port RAM 128 x 18 bit FIFO 128 x 36 bit TriMatrix memory M-RAM block Single port RAM 4K x 144 bit Simple dual-port RAM 4K x 144 bit True dual-port RAM 4K x 144 bit Single port RAM 8K x 72 bit Simple dual-port RAM 8K x 72 bit True dual-port RAM 8K x 72 bit Single port RAM 16K x 36 bit Simple dual-port RAM 16K x 36 bit
0 0
1 1
0 0
278.94 255.95
243.19 223.06
211.59 194.06
179.82 164.93
MHz MHz
0
1
0
255.95
223.06
194.06
164.93
MHz
0 0
1 1
0 0
280.66 269.83
254.32 237.69
221.28 206.82
188.00 175.74
MHz MHz
4-20 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-36. Stratix Performance (Part 2 of 2) Notes (1), (2) Resources Used Applications TriMatrix DSP LEs Memory Blocks Blocks
0 1 0
Performance -5 Speed Grade
269.83
-6 Speed Grade
237.69
-7 Speed Grade
206.82
-8 Speed Grade
175.74
Units
MHz
TriMatrix memory M-RAM block
True dual-port RAM 16K x 36 bit Single port RAM 32K x 18 bit Simple dual-port RAM 32K x 18 bit True dual-port RAM 32K x 18 bit Single port RAM 64K x 9 bit Simple dual-port RAM 64K x 9 bit True dual-port RAM 64K x 9 bit
0 0
1 1
0 0
275.86 275.86
244.55 244.55
212.76 212.76
180.83 180.83
MHz MHz
0
1
0
275.86
244.55
212.76
180.83
MHz
0 0
1 1
0 0
287.85 287.85
253.29 253.29
220.36 220.36
187.26 187.26
MHz MHz
0
1
0
287.85
253.29
220.36
187.26
MHz
DSP block
9 x 9-bit multiplier (3) 18 x 18-bit multiplier (4) 36 x 36-bit multiplier (4) 36 x 36-bit multiplier (5) 18-bit, 4-tap FIR filter
0 0 0 0 0 58 870
0 0 0 0 0 0 5
1 1 1 1 1 4 1
335.0 278.78 148.25 278.78 278.78 141.26 261.09
293.94 237.41 134.71 237.41 237.41 133.49 235.51
255.68 206.52 117.16 206.52 206.52 114.88 205.21
217.24 175.50 99.59 175.5 175.50 100.28 175.22
MHz MHz MHz MHz MHz MHz MHz
Larger Designs
8-bit, 16-tap parallel FIR filter 8-bit, 1,024-point FFT function
Notes to Table 4-36:
(1) (2) (3) (4) (5) These design performance numbers were obtained using the Quartus II software. Numbers not listed will be included in a future version of the data sheet. This application uses registered inputs and outputs. This application uses registered multiplier input and output stages within the DSP block. This application uses registered multiplier input, pipeline, and output stages within the DSP block.
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4-21 Stratix Device Handbook, Volume 1
Timing Model
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis independent of device density. Tables 4-37 through 4-42 describe the Stratix device internal timing microparameters for LEs, IOEs, TriMatrixTM memory structures, DSP blocks, and MultiTrack interconnects.
Table 4-37. LE Internal Timing Microparameter Descriptions Symbol
tSU tH tCO tLUT tCLR tPRE tCLKHL
Parameter
LE register setup time before clock LE register hold time after clock LE register clock-to-output delay LE combinatorial LUT delay for data-in to data-out Minimum clear pulse width Minimum preset pulse width Register minimum clock high or low time. The maximum core clock frequency can be calculated by 1/(2 x tCLKHL).
Table 4-38. IOE Internal Timing Microparameter Descriptions Symbol
tSU_R tSU_C tH tCO_R tC O _ C tPIN2COMBOUT_R tPIN2COMBOUT_C tCOMBIN2PIN_R tCOMBIN2PIN_C tCLR tPRE tCLKHL
Parameter
Row IOE input register setup time Column IOE input register setup time IOE input and output register hold time after clock Row IOE input and output register clock-to-output delay Column IOE input and output register clock-to-output delay Row input pin to IOE combinatorial output Column input pin to IOE combinatorial output Row IOE data input to combinatorial output pin Column IOE data input to combinatorial output pin Minimum clear pulse width Minimum preset pulse width Register minimum clock high or low time. The maximum I/O clock frequency can be calculated by 1/(2 x tCLKHL). Performance may also be affected by I/O timing, use of PLL, and I/O programmable settings.
4-22 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-39. DSP Block Internal Timing Microparameter Descriptions Symbol
tSU tH tCO tINREG2PIPE9 tINREG2PIPE18 tPIPE2OUTREG2ADD tPIPE2OUTREG4ADD tPD9 tPD18 tPD36 tCLR tCLKHL
Parameter
Input, pipeline, and output register setup time before clock Input, pipeline, and output register hold time after clock Input, pipeline, and output register clock-to-output delay Input Register to DSP Block pipeline register in 9 x 9-bit mode Input Register to DSP Block pipeline register in 18 x 18-bit mode DSP Block Pipeline Register to output register delay in TwoMultipliers Adder mode DSP Block Pipeline Register to output register delay in FourMultipliers Adder mode Combinatorial input to output delay for 9 x 9 Combinatorial input to output delay for 18 x 18 Combinatorial input to output delay for 36 x 36 Minimum clear pulse width Register minimum clock high or low time. This is a limit on the min time for the clock on the registers in these blocks. The actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown in Table 4-36 on page 4-20 and as reported by the timing analyzer in the Quartus II software.
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4-23 Stratix Device Handbook, Volume 1
Timing Model
Table 4-40. M512 Block Internal Timing Microparameter Descriptions Symbol
tM512RC tM512WC tM512WERESU tM512WEREH tM512CLKENSU tM512CLKENH tM512DATASU tM512DATAH tM512WADDRSU tM512WADDRH tM512RADDRSU tM512RADDRH tM512DATACO1 tM512DATACO2 tM512CLKHL
Parameter
Synchronous read cycle time Synchronous write cycle time Write or read enable setup time before clock Write or read enable hold time after clock Clock enable setup time before clock Clock enable hold time after clock Data setup time before clock Data hold time after clock Write address setup time before clock Write address hold time after clock Read address setup time before clock Read address hold time after clock Clock-to-output delay when using output registers Clock-to-output delay without output registers Register minimum clock high or low time. This is a limit on the min time for the clock on the registers in these blocks. The actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown in Table 4-36 on page 4-20 and as reported by the timing analyzer in the Quartus II software. Minimum clear pulse width
tM512CLR
Table 4-41. M4K Block Internal Timing Microparameter Descriptions (Part 1 of 2) Symbol
tM4KRC tM4KWC tM4KWERESU tM4KWEREH tM4KCLKENSU tM4KCLKENH tM4KBESU tM4KBEH tM4KDATAASU
Parameter
Synchronous read cycle time Synchronous write cycle time Write or read enable setup time before clock Write or read enable hold time after clock Clock enable setup time before clock Clock enable hold time after clock Byte enable setup time before clock Byte enable hold time after clock A port data setup time before clock
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Altera Corporation July 2005
DC & Switching Characteristics
Table 4-41. M4K Block Internal Timing Microparameter Descriptions (Part 2 of 2) Symbol
tM4KDATAAH tM4KADDRASU tM4KADDRAH tM4KDATABSU tM4KDATABH tM4KADDRBSU tM4KADDRBH tM4KDATACO1 tM4KDATACO2 tM4KCLKHL
Parameter
A port data hold time after clock A port address setup time before clock A port address hold time after clock B port data setup time before clock B port data hold time after clock B port address setup time before clock B port address hold time after clock Clock-to-output delay when using output registers Clock-to-output delay without output registers Register minimum clock high or low time. This is a limit on the min time for the clock on the registers in these blocks. The actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown inTable 4-36 on page 4-20 and as reported by the timing analyzer in the Quartus II software. Minimum clear pulse width
tM4KCLR
Table 4-42. M-RAM Block Internal Timing Microparameter Descriptions (Part 1 of 2) Symbol
tMRAMRC tMRAMWC tMRAMWERESU tMRAMWEREH tMRAMCLKENSU tMRAMCLKENH tMRAMBESU tMRAMBEH tMRAMDATAASU tMRAMDATAAH tMRAMADDRASU tMRAMADDRAH tMRAMDATABSU
Parameter
Synchronous read cycle time Synchronous write cycle time Write or read enable setup time before clock Write or read enable hold time after clock Clock enable setup time before clock Clock enable hold time after clock Byte enable setup time before clock Byte enable hold time after clock A port data setup time before clock A port data hold time after clock A port address setup time before clock A port address hold time after clock B port setup time before clock
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Timing Model
Table 4-42. M-RAM Block Internal Timing Microparameter Descriptions (Part 2 of 2) Symbol
tMRAMDATABH tMRAMADDRBSU tMRAMADDRBH tMRAMDATACO1 tMRAMDATACO2 tMRAMCLKHL
Parameter
B port hold time after clock B port address setup time before clock B port address hold time after clock Clock-to-output delay when using output registers Clock-to-output delay without output registers Register minimum clock high or low time. This is a limit on the min time for the clock on the registers in these blocks. The actual performance is dependent upon the internal point-to-point delays in the blocks and may give slower performance as shown in Table 4-36 on page 4-20 and as reported by the timing analyzer in the Quartus II software. Minimum clear pulse width.
tMRAMCLR
4-26 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Figure 4-3 shows the TriMatrix memory waveforms for the M512, M4K, and M-RAM timing parameters shown in Tables 4-40 through 4-42. Figure 4-3. Dual-Port RAM Timing Microparameter Waveform
wrclock tWEREH wren tWADDRSU wraddress an-1 tDATAH data-in din-1 tDATASU rdclock tWERESU rden tRC rdaddress bn b0 tDATACO1 reg_data-out doutn-2 doutn-1 tDATACO2 unreg_data-out doutn-1 doutn dout0 doutn dout0 b1 b2 b3 tWEREH din din4 din5 din6 an a0 a1 a2 a3 a4 tWADDRH a5 a6 tWERESU
Internal timing parameters are specified on a speed grade basis independent of device density. Tables 4-44 through 4-50 show the internal timing microparameters for LEs, IOEs, TriMatrix memory structures, DSP blocks, and MultiTrack interconnects.
Table 4-43. Routing Delay Internal Timing Microparameter Descriptions (Part 1 of 2) Symbol
tR4 tR8 tR24
Parameter
Delay for an R4 line with average loading; covers a distance of four LAB columns. Delay for an R8 line with average loading; covers a distance of eight LAB columns. Delay for an R24 line with average loading; covers a distance of 24 LAB columns.
Altera Corporation July 2005
4-27 Stratix Device Handbook, Volume 1
Timing Model
Table 4-43. Routing Delay Internal Timing Microparameter Descriptions (Part 2 of 2) Symbol
tC4 tC8 tC16 tLOCAL
Parameter
Delay for a C4 line with average loading; covers a distance of four LAB rows. Delay for a C8 line with average loading; covers a distance of eight LAB rows. Delay for a C16 line with average loading; covers a distance of 16 LAB rows. Local interconnect delay, for connections within a LAB, and for the final routing hop of connections to LABs, DSP blocks, RAM blocks and I/Os.
Table 4-44. LE Internal Timing Microparameters -5 Parameter Min
tSU tH tCO tLUT tCLR tPRE tCLKHL 100 100 1000 10 100 156 366 100 100 1111
-6 Max Min
10 100 176 459 114 114 1190
-7 Max Min
11 114 202 527 135 135 1400
-8 Unit Max Min
13 135 238 621
Max
ps ps ps ps ps ps ps
Table 4-45. IOE Internal TSU Microparameter by Device Density (Part 1 of 2) -5 Device
EP1S10
-6 Max Min
80 80 80 80 280 280 80 180
-7 Max Min
80 80 80 80 280 280 80 180
-8 Max Min
80 80 80 80 280 280 80 180
Unit Max
ps ps ps ps ps ps ps ps
Symbol Min
tSU_R tSU_C 76 176 76 76 276 276 76 176
EP1S20
tSU_R tSU_C
EP1S25
tSU_R tSU_C
EP1S30
tSU_R tSU_C
4-28 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-45. IOE Internal TSU Microparameter by Device Density (Part 2 of 2) -5 Device
EP1S40
-6 Max Min
80 380 280 280 430 80
-7 Max Min
80 380 280 280 430 80
-8 Max Min
80 380 280 280 430 80
Unit Max
ps ps ps ps ps ps
Symbol Min
tSU_R tSU_C 76 376 276 276 426 76
EP1S60
tSU_R tS U _ C
EP1S80
tSU_R tSU_C
Table 4-46. IOE Internal Timing Microparameters -5 Symbol Min
tH tCO_R tCO_C tPIN2COMBOUT_R tPIN2COMBOUT_C tCOMBIN2PIN_R tCOMBIN2PIN_C tCLR tPRE tCLKHL 276 260 1,000 68 171 171 1,234 1,087 3,894 4,299 289 273 1,111
-6 Max Min
71 179 179 1,295 1,141 4,089 4,494 333 313 1,190
-7 Max Min
82 206 206 1,490 1,312 4,089 4,494 392 369 1,400
-8 Unit Max Min
96 242 242 1,753 1,544 4,089 4,494
Max
ps ps ps ps ps ps ps ps ps ps
Table 4-47. DSP Block Internal Timing Microparameters (Part 1 of 2) -5 Symbol Min
tSU tH tCO tINREG2PIPE9 tINREG2PIPE18 0 67 142 2,613 3,390
-6 Max Min
0 75 158 2,982 3,993
-7 Max Min
0 86 181 3,429 4,591
-8 Unit Max Min
0 101 214 4,035 5,402
Max
ps ps ps ps ps
Altera Corporation July 2005
4-29 Stratix Device Handbook, Volume 1
Timing Model
Table 4-47. DSP Block Internal Timing Microparameters (Part 2 of 2) -5 Symbol Min
tPIPE2OUTREG2ADD tPIPE2OUTREG4ADD tPD9 tPD18 tPD36 tCLR tCLKHL 450 1,350
-6 Max
2,002 2,899 3,709 4,795 7,495 500 1,500
-7 Max
2,203 3,189 4,081 5,275 8,245 575 1,724
-8 Unit Max
2,533 3,667 4,692 6,065 9,481 676 2,029
Min
Min
Min
Max
2,980 4,314 5,520 7,135 11,154 ps ps ps ps ps ps ps
Table 4-48. M512 Block Internal Timing Microparameters -5 Symbol Min
tM512RC tM512WC tM512WERESU tM512WEREH tM512CLKENSU tM512CLKENH tM512DATASU tM512DATAH tM512WADDRSU tM512WADDRH tM512RADDRSU tM512RADDRH tM512DATACO1 tM512DATACO2 tM512CLKHL tM512CLR 1,000 170 110 34 215 -70 110 34 110 34 110 34 424 3,366 1,111 189
-6 Max
3,340 3,138 123 38 215 -70 123 38 123 38 123 38 472 3,846 1,190 217
-7 Max
3,816 3,590 141 43 247 -81 141 43 141 43 141 43 541 4,421 1,400 255
-8 Unit Max
4,387 4,128 166 51 290 -95 166 51 166 51 166 51 637 5,203
Min
Min
Min
Max
5,162 4,860 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
4-30 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-49. M4K Block Internal Timing Microparameters -5 Symbol Min
tM4KRC tM4KWC tM4KWERESU tM4KWEREH tM4KCLKENSU tM4KCLKENH tM4KBESU tM4KBEH tM4KDATAASU tM4KDATAAH tM4KADDRASU tM4KADDRAH tM4KDATABSU tM4KDATABH tM4KADDRBSU tM4KADDRBH tM4KDATACO1 tM4KDATACO2 tM4KCLKHL tM4KCLR 1,000 170 131 34 193 -63 131 34 131 34 131 34 131 34 131 34 571 3,984 1,111 189
-6 Max
3,807 2,556 149 38 215 -70 149 38 149 38 149 38 149 38 149 38 635 4,507 1,190 217
-7 Max
4,320 2,840 171 43 247 -81 171 43 171 43 171 43 171 43 171 43 729 5,182 1,400 255
-8 Unit Max
4,967 3,265 202 51 290 -95 202 51 202 51 202 51 202 51 202 51 858 6,097
Min
Min
Min
Max
5,844 3,842 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Table 4-50. M-RAM Block Internal Timing Microparameters (Part 1 of 2) -5 Symbol Min
tMRAMRC tMRAMWC tMRAMWERESU tMRAMWEREH tMRAMCLKENSU tMRAMCLKENH 25 18 99 -48
-6 Max
4,364 3,654 25 20 111 -53
-7 Max
4,838 4,127 28 23 127 -61
-8 Unit Max
5,562 4,746 33 27 150 -72
Min
Min
Min
Max
6,544 5,583 ps ps ps ps ps ps
Altera Corporation July 2005
4-31 Stratix Device Handbook, Volume 1
Timing Model
Table 4-50. M-RAM Block Internal Timing Microparameters (Part 2 of 2) -5 Symbol Min
tMRAMBESU tMRAMBEH tMRAMDATAASU tMRAMDATAAH tMRAMADDRASU tMRAMADDRAH tMRAMDATABSU tMRAMDATABH tMRAMADDRBSU tMRAMADDRBH tMRAMDATACO1 tMRAMDATACO2 tMRAMCLKHL tMRAMCLR 1,000 135 25 18 25 18 25 18 25 18 25 18 1,038 4,362 1,111 150
-6 Max Min
25 20 25 20 25 20 25 20 25 20 1,053 4,939 1,190 172
-7 Max Min
28 23 28 23 28 23 28 23 28 23 1,210 5,678 1,400 202
-8 Unit Max Min
33 27 33 27 33 27 33 27 33 27 1,424 6,681
Max
ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Table 4-51. Routing Delay Internal Timing Parameters -5 Symbol Min
tR 4 tR 8 tR 2 4 tC 4 tC 8 tC 1 6 tL O C A L
-6 Max Min Max
295 349 512 484 634 489 345
-7 Min Max
339 401 588 557 730 563 396
-8 Min Max
390 461 676 641 840 647 455 ps ps ps ps ps ps ps
Unit
268 371 465 440 577 445 313
Routing delays vary depending on the load on that specific routing line. The Quartus II software reports the routing delay information when running the timing analysis for a design.
4-32 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
External Timing Parameters
External timing parameters are specified by device density and speed grade. Figure 4-4 shows the pin-to-pin timing model for bidirectional IOE pin timing. All registers are within the IOE. Figure 4-4. External Timing in Stratix Devices
OE Register
D PRN Q
Dedicated Clock
CLRN
Output Register
D PRN Q
tINSU tINH tOUTCO tXZ tZX Bidirectional Pin
CLRN
Input Register
D PRN Q
CLRN
All external timing parameters reported in this section are defined with respect to the dedicated clock pin as the starting point. All external I/O timing parameters shown are for 3.3-V LVTTL I/O standard with the 24-mA current strength and fast slew rate. For external I/O timing using standards other than LVTTL or for different current strengths, use the I/O standard input and output delay adders in Tables 4-103 through 4-108.
Altera Corporation July 2005
4-33 Stratix Device Handbook, Volume 1
Timing Model
Table 4-52 shows the external I/O timing parameters when using fast regional clock networks.
Table 4-52. Stratix Fast Regional Clock External I/O Timing Parameters Notes (1), (2) Symbol
tINSU tINH tOUTCO tXZ tZX
Parameter
Setup time for input or bidirectional pin using IOE input register with fast regional clock fed by FCLK pin Hold time for input or bidirectional pin using IOE input register with fast regional clock fed by FCLK pin Clock-to-output delay output or bidirectional pin using IOE output register with fast regional clock fed by FCLK pin Synchronous IOE output enable register to output pin disable delay using fast regional clock fed by FCLK pin Synchronous IOE output enable register to output pin enable delay using fast regional clock fed by FCLK pin
Notes to Table 4-52:
(1) (2) These timing parameters are sample-tested only. These timing parameters are for column and row IOE pins. You should use the Quartus II software to verify the external timing for any pin.
Table 4-53 shows the external I/O timing parameters when using regional clock networks.
Table 4-53. Stratix Regional Clock External I/O Timing Parameters (Part 1 of 2) Notes (1), (2) Symbol
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL
Parameter
Setup time for input or bidirectional pin using IOE input register with regional clock fed by CLK pin Hold time for input or bidirectional pin using IOE input register with regional clock fed by CLK pin Clock-to-output delay output or bidirectional pin using IOE output register with regional clock fed by CLK pin Setup time for input or bidirectional pin using IOE input register with regional clock fed by Enhanced PLL with default phase setting Hold time for input or bidirectional pin using IOE input register with regional clock fed by Enhanced PLL with default phase setting Clock-to-output delay output or bidirectional pin using IOE output register with regional clock Enhanced PLL with default phase setting
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Altera Corporation July 2005
DC & Switching Characteristics
Table 4-53. Stratix Regional Clock External I/O Timing Parameters (Part 2 of 2) Notes (1), (2) Symbol
tXZPLL tZXPLL
Parameter
Synchronous IOE output enable register to output pin disable delay using regional clock fed by Enhanced PLL with default phase setting Synchronous IOE output enable register to output pin enable delay using regional clock fed by Enhanced PLL with default phase setting
Notes to Table 4-53:
(1) (2) These timing parameters are sample-tested only. These timing parameters are for column and row IOE pins. You should use the Quartus II software to verify the external timing for any pin.
Table 4-54 shows the external I/O timing parameters when using global clock networks.
Table 4-54. Stratix Global Clock External I/O Timing Parameters Notes (1), (2) Symbol
tINSU tINH tOUTCO tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL
Parameter
Setup time for input or bidirectional pin using IOE input register with global clock fed by CLK pin Hold time for input or bidirectional pin using IOE input register with global clock fed by CLK pin Clock-to-output delay output or bidirectional pin using IOE output register with global clock fed by CLK pin Setup time for input or bidirectional pin using IOE input register with global clock fed by Enhanced PLL with default phase setting Hold time for input or bidirectional pin using IOE input register with global clock fed by Enhanced PLL with default phase setting Clock-to-output delay output or bidirectional pin using IOE output register with global clock Enhanced PLL with default phase setting Synchronous IOE output enable register to output pin disable delay using global clock fed by Enhanced PLL with default phase setting Synchronous IOE output enable register to output pin enable delay using global clock fed by Enhanced PLL with default phase setting
Notes to Table 4-54:
(1) (2) These timing parameters are sample-tested only. These timing parameters are for column and row IOE pins. You should use the Quartus II software to verify the external timing for any pin.
Altera Corporation July 2005
4-35 Stratix Device Handbook, Volume 1
Timing Model
Stratix External I/O Timing
These timing parameters are for both column IOE and row IOE pins. In EP1S30 devices and above, you can decrease the tSU time by using the FPLLCLK, but may get positive hold time in EP1S60 and EP1S80 devices. You should use the Quartus II software to verify the external devices for any pin. Tables 4-55 through 4-60 show the external timing parameters on column and row pins for EP1S10 devices.
Table 4-55. EP1S10 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX 2.238 0.000 2.240 2.180 2.180 4.549 4.423 4.423
-6 Speed Grade Min
2.325 0.000 2.240 2.180 2.180 4.836 4.704 4.704
-7 Speed Grade Min
2.668 0.000 2.240 2.180 2.180 5.218 5.094 5.094
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
Table 4-56. EP1S10 External I/O Timing on Column Pins Using Regional Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.992 0.000 2.395 2.335 2.335 0.975 0.000 1.262 1.202 1.202 2.636 2.510 2.510 4.795 4.669 4.669
-6 Speed Grade Min
2.054 0.000 2.395 2.335 2.335 0.985 0.000 1.262 1.202 1.202 2.680 2.548 2.548 5.107 4.975 4.975
-7 Speed Grade Min
2.359 0.000 2.395 2.335 2.335 1.097 0.000 1.262 1.202 1.202 2.769 2.645 2.645 5.527 5.403 5.403
-8 Speed Grade Unit
Max
Max
Max
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA ns ns ns ns ns ns ns ns ns ns
4-36 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-57. EP1S10 External I/O Timing on Column Pins Using Global Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.647 0.000 2.619 2.559 2.559 1.239 0.000 1.109 1.049 1.049 2.372 2.246 2.246 5.184 5.058 5.058
-6 Speed Grade Min
1.692 0.000 2.619 2.559 2.559 1.229 0.000 1.109 1.049 1.049 2.436 2.304 2.304 5.515 5.383 5.383
-7 Speed Grade Min
1.940 0.000 2.619 2.559 2.559 1.374 0.000 1.109 1.049 1.049 2.492 2.368 2.368 5.999 5.875 5.875
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-58. EP1S10 External I/O Timing on Row Pin Using Fast Regional Clock Network Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX 2.212 0.000 2.391 2.418 2.418 4.838 4.892 4.892
-6 Speed Grade Min
2.403 0.000 2.391 2.418 2.418 5.159 5.215 5.215
-7 Speed Grade Min
2.759 0.000 2.391 2.418 2.418 5.569 5.637 5.637
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
Altera Corporation July 2005
4-37 Stratix Device Handbook, Volume 1
Timing Model
Table 4-59. EP1S10 External I/O Timing on Row Pins Using Regional Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 2.161 0.000 2.434 2.461 2.461 1.057 0.000 1.327 1.354 1.354 2.773 2.827 2.827 4.889 4.493 4.493
-6 Speed Grade Min
2.336 0.000 2.434 2.461 2.461 1.172 0.000 1.327 1.354 1.354 2.848 2.904 2.904 5.226 5.282 5.282
-7 Speed Grade Min
2.685 0.000 2.434 2.461 2.461 1.315 0.000 1.327 1.354 1.354 2.940 3.008 3.008 5.643 5.711 5.711
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-60. EP1S10 External I/O Timing on Row Pins Using Global Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL
(1)
-6 Speed Grade Min
1.944 0.000
-7 Speed Grade Min
2.232 0.000
-8 Speed Grade Unit Min
NA NA
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
1.787 0.000 2.647 2.674 2.674 1.371 0.000 1.144 1.171 1.171 2.459 2.513 2.513 5.263 5.317 5.317
2.647 2.674 2.674 1.1472 0.000 1.144 1.171 1.171
5.618 5.674 5.674
2.647 2.674 2.674 1.654 0.000
6.069 6.164 6.164
NA NA NA NA NA
2.548 2.604 2.604
1.144 1.171 1.171
2.601 2.669 2.669
NA NA NA
Note to Tables 4-55 to 4-60:
Only EP1S25, EP1S30, and EP1S40 have speed grade of -8.
4-38 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Tables 4-61 through 4-66 show the external timing parameters on column and row pins for EP1S20 devices.
Table 4-61. EP1S20 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX 2.065 0.000 2.283 2.223 2.223 4.622 4.496 4.496
-6 Speed Grade Min
2.245 0.000 2.283 2.223 2.223 4.916 4.784 4.784
-7 Speed Grade Min
2.576 0.000 2.283 2.223 2.223 5.310 5.186 5.186
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
Table 4-62. EP1S20 External I/O Timing on Column Pins Using Regional Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.541 0.000 2.597 2.537 2.537 0.777 0.000 1.296 1.236 1.236 2.690 2.564 2.564 5.146 5.020 5.020
-6 Speed Grade Min
1.680 0.000 2.597 2.537 2.537 0.818 0.000 1.296 1.236 1.236 2.801 2.669 2.669 5.481 5.349 5.349
-7 Speed Grade Min
1.931 0.000 2.597 2.537 2.537 0.937 0.000 1.296 1.236 1.236 2.876 2.752 2.752 5.955 5.831 5.831
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Altera Corporation July 2005
4-39 Stratix Device Handbook, Volume 1
Timing Model
Table 4-63. EP1S20 External I/O Timing on Column Pins Using Global Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.351 0.000 2.732 2.672 2.672 0.923 0.000 1.210 1.150 1.150 2.544 2.418 2.418 5.380 5.254 5.254
-6 Speed Grade Min
1.479 0.000 2.732 2.672 2.672 0.971 0.000 1.210 1.150 1.150 2.648 2.516 2.516 5.728 5.596 5.596
-7 Speed Grade Min
1.699 0.000 2.732 2.672 2.672 1.098 0.000 1.210 1.150 1.150 2.715 2.591 2.591 6.240 6.116 6.116
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-64. EP1S20 External I/O Timing on Row Pins Using Fast Regional Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX 2.032 0.000 2.492 2.519 2.519 5.018 5.072 5.072
-6 Speed Grade Min
2.207 0.000 2.492 2.519 2.519 5.355 5.411 5.411
-7 Speed Grade Min
2.535 0.000 2.492 2.519 2.519 5.793 5.861 5.861
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
4-40 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-65. EP1S20 External I/O Timing on Row Pins Using Regional Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.815 0.000 2.633 2.660 2.660 1.060 0.000 1.325 1.352 1.352 2.770 2.824 2.824 5.235 5.289 5.289
-6 Speed Grade Min
1.967 0.000 2.663 2.660 2.660 1.112 0.000 1.325 1.352 1.352 2.908 2.964 2.964 5.595 5.651 5.651
-7 Speed Grade Min
2.258 0.000 2.663 2.660 2.660 1.277 0.000 1.325 1.352 1.352 2.978 3.046 3.046 6.070 6.138 6.138
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-66. EP1S20 External I/O Timing on Row Pins Using Global Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL
(1)
-6 Speed Grade Min
1.887 0.000
-7 Speed Grade Min
2.170 0.000
-8 Speed Grade Unit Min
NA NA
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
1.742 0.000 2.674 2.701 2.701 1.353 0.000 1.158 1.185 1.185 2.447 2.531 2.531 5.308 5.362 5.362
2.674 2.701 2.701 1.418 0.000 1.158 1.158 1.158
5.675 5.731 5.731
2.674 2.701 2.701 1.613 0.000
6.158 6.226 6.226
NA NA NA NA NA
2.602 2.602 2.602
1.158 1.185 1.185
2.642 2.710 2.710
NA NA NA
Note to Tables 4-61 to 4-66:
Only EP1S25, EP1S30, and EP1S40 have a speed grade of -8.
Altera Corporation July 2005
4-41 Stratix Device Handbook, Volume 1
Timing Model
Tables 4-67 through 4-72 show the external timing parameters on column and row pins for EP1S25 devices.
Table 4-67. EP1S25 External I/O Timing on Column Pins Using Fast Regional Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX 2.412 0.000 2.196 2.136 2.136 4.475 4.349 4.349
-6 Speed Grade Min
2.613 0.000 2.196 2.136 2.136 4.748 4.616 4.616
-7 Speed Grade Min
2.968 0.000 2.196 2.136 2.136 5.118 4.994 4.994
-8 Speed Grade Unit Min
3.468 0.000 2.196 2.136 2.136 5.603 5.488 5.488
Max
Max
Max
Max
ns ns ns ns ns
Table 4-68. EP1S25 External I/O Timing on Column Pins Using Regional Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.535 0.000 2.739 2.679 2.679 0.934 0.000 1.316 1.256 1.256 2.733 2.607 2.607 5.396 5.270 5.270
-6 Speed Grade Min
1.661 0.000 2.739 2.679 2.679 0.980 0.000 1.316 1.256 1.256 2.839 2.707 2.707 5.746 5.614 5.614
-7 Speed Grade Min
1.877 0.000 2.739 2.679 2.679 1.092 0.000 1.316 1.256 1.256 2.921 2.797 2.797 6.262 6.138 6.138
-8 Speed Grade Unit Min
2.125 0.000 2.739 2.679 2.679 1.231 0.000 1.316 1.256 1.256 3.110 2.995 2.995 6.946 6.831 6.831
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
4-42 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-69. EP1S25 External I/O Timing on Column Pins Using Global Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.371 0.000 2.809 2.749 2.749 1.271 0.000 1.124 1.064 1.064 2.396 2.270 2.270 5.516 5.390 5.390
-6 Speed Grade Min
1.471 0.000 2.809 2.749 2.749 1.327 0.000 1.124 1.064 1.064 2.492 2.360 2.360 5.890 5.758 5.758
-7 Speed Grade Min
1.657 0.000 2.809 2.749 2.749 1.491 0.000 1.124 1.064 1.064 2.522 2.398 2.398 6.429 6.305 6.305
-8 Speed Grade Unit Min
1.916 0.000 2.809 2.749 2.749 1.677 0.000 1.124 1.064 1.064 2.602 2.487 2.487 7.155 7.040 7.040
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-70. EP1S25 External I/O Timing on Row Pins Using Fast Regional Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX 2.429 0.000 2.376 2.403 2.403 4.821 4.875 4.875
-6 Speed Grade Min
2.631 0.000 2.376 2.403 2.403 5.131 5.187 5.187
-7 Speed Grade Min
2.990 0.000 2.376 2.403 2.403 5.538 5.606 5.606
-8 Speed Grade Unit Min
3.503 0.000 2.376 2.403 2.403 6.063 6.145 6.145
Max
Max
Max
Max
ns ns ns ns ns
Altera Corporation July 2005
4-43 Stratix Device Handbook, Volume 1
Timing Model
Table 4-71. EP1S25 External I/O Timing on Row Pins Using Regional Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.793 0.000 2.759 2.786 2.786 1.169 0.000 1.375 1.402 1.402 2.861 2.915 2.915 5.457 5.511 5.511
-6 Speed Grade Min
1.927 0.000 2.759 2.786 2.786 1.221 0.000 1.375 1.402 1.402 2.999 3.055 3.055 5.835 5.891 5.891
-7 Speed Grade Min
2.182 0.000 2.759 2.786 2.786 1.373 0.000 1.375 1.402 1.402 3.082 3.150 3.150 6.346 6.414 6.414
-8 Speed Grade Unit Min
2.542 0.000 2.759 2.786 2.786 1.600 0.000 1.375 1.402 1.402 3.174 3.256 3.256 7.024 7.106 7.106
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-72. EP1S25 External I/O Timing on Row Pins Using Global Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.665 0.000 2.834 2.861 2.861 1.538 0.000 1.164 1.191 1.191 2.492 2.546 2.546 5.585 5.639 5.639
-6 Speed Grade Min
1.779 0.000 2.834 2.861 2.861 1.606 0.000 1.164 1.191 1.191 2.614 2.670 2.670 5.983 6.039 6.039
-7 Speed Grade Min
2.012 0.000 2.834 2.861 2.861 1.816 0.000 1.164 1.191 1.191 2.639 2.707 2.707 6.516 6.584 6.584
-8 Speed Grade Unit Min
2.372 0.000 2.834 2.861 2.861 2.121 0.000 1.164 1.191 1.191 2.653 2.735 2.735 7.194 7.276 7.276
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
4-44 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Tables 4-73 through 4-78 show the external timing parameters on column and row pins for EP1S30 devices.
Table 4-73. EP1S30 External I/O Timing on Column Pins Using Fast Regional Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX 2.502 0.000 2.473 2.413 2.413 4.965 4.839 4.839
-6 Speed Grade Min
2.680 0.000 2.473 2.413 2.413 5.329 5.197 5.197
-7 Speed Grade Min
3.062 0.000 2.473 2.413 2.413 5.784 5.660 5.660
-8 Speed Grade Min
3.591 0.000 2.473 2.413 2.413 6.392 6.277 6.277
Unit
Max
Max
Max
Max
ns ns ns ns ns
Table 4-74. EP1S30 External I/O Timing on Column Pins Using Regional Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 2.286 0.000 2.641 2.581 2.581 1.200 0.000 1.108 1.048 1.048 2.367 2.241 2.241 5.225 5.099 5.099
-6 Speed Grade Min
2.426 0.000 2.641 2.581 2.581 1.185 0.000 1.108 1.048 1.048 2.534 2.402 2.402 5.629 5.497 5.497
-7 Speed Grade Min
2.769 0.000 2.641 2.581 2.581 1.344 0.000 1.108 1.048 1.048 2.569 2.445 2.445 6.130 6.006 6.006
-8 Speed Grade Unit Min
3.249 0.000 2.641 2.581 2.581 1.662 0.000 1.108 1.048 1.048 2.517 2.402 2.402 6.796 6.681 6.681
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-75. EP1S30 External I/O Timing on Column Pins Using Global Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO 1.935 0.000 2.814 5.532
(Part 1 of 2) Unit
-6 Speed Grade Min
2.029 0.000 2.814 5.980
-7 Speed Grade Min
2.310 0.000 2.814 6.536
-8 Speed Grade Min
2.709 0.000 2.814 7.274
Max
Max
Max
Max
ns ns ns
Altera Corporation July 2005
4-45 Stratix Device Handbook, Volume 1
Timing Model
Table 4-75. EP1S30 External I/O Timing on Column Pins Using Global Clock Networks -5 Speed Grade Parameter Min
tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 2.754 2.754 1.265 0.000 1.068 1.008 1.008 2.302 2.176 2.176
(Part 2 of 2) Unit
-6 Speed Grade Min
2.754 2.754 1.236 0.000 1.068 1.008 1.008 2.483 2.351 2.351
-7 Speed Grade Min
2.754 2.754 1.403 0.000 1.068 1.008 1.008 2.510 2.386 2.386
-8 Speed Grade Min
2.754 2.754 1.756 0.000 1.068 1.008 1.008 2.423 2.308 2.308
Max
5.406 5.406
Max
5.848 5.848
Max
6.412 6.412
Max
7.159 7.159 ns ns ns ns ns ns ns
Table 4-76. EP1S30 External I/O Timing on Row Pins Using Fast Regional Clock Networks -5 Speed Grade Parameters Min
tINSU tINH tOUTCO tXZ tZX 2.616 0.000 2.542 2.569 2.569 5.114 5.168 5.168
-6 Speed Grade Min
2.808 0.000 2.542 2.569 2.569 5.502 5.558 5.558
-7 Speed Grade Min
3.223 0.000 2.542 2.569 2.569 5.965 6.033 6.033
-8 Speed Grade Unit Min
3.797 0.000 2.542 2.569 2.569 6.581 6.663 6.663
Max
Max
Max
Max
ns ns ns ns ns
4-46 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-77. EP1S30 External I/O Timing on Row Pins Using Regional Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 2.322 0.000 2.731 2.758 2.758 1.291 0.000 1.192 1.219 1.219 2.539 2.539 2.539 5.408 5.462 5.462
-6 Speed Grade Min
2.467 0.000 2.731 2.758 2.758 1.283 0.000 1.192 1.219 1.219 2.737 2.793 2.793 5.843 5.899 5.899
-7 Speed Grade Min
2.828 0.000 2.731 2.758 2.758 1.469 0.000 1.192 1.219 1.219 2.786 2.854 2.854 6.360 6.428 6.428
-8 Speed Grade Unit Min
3.342 0.000 2.731 2.758 2.758 1.832 0.000 1.192 1.219 1.219 2.742 2.824 2.824 7.036 7.118 7.118
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-78. EP1S30 External I/O Timing on Row Pins Using Global Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.995 0.000 2.917 2.944 2.944 1.337 0.000 1.164 1.191 1.191 2.493 2.547 2.547 5.735 5.789 5.789
-6 Speed Grade Min
2.089 0.000 2.917 2.944 2.944 1.312 0.000 1.164 1.191 1.191 2.708 2.764 2.764 6.221 6.277 6.277
-7 Speed Grade Min
2.398 0.000 2.917 2.944 2.944 1.508 0.000 1.164 1.191 1.191 2.747 2.815 2.815 6.790 6.858 6.858
-8 Speed Grade Unit Min
2.830 0.000 2.917 2.944 2.944 1.902 0.000 1.164 1.191 1.191 2.672 2.754 2.754 7.548 7.630 7.630
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Altera Corporation July 2005
4-47 Stratix Device Handbook, Volume 1
Timing Model
Tables 4-79 through 4-84 show the external timing parameters on column and row pins for EP1S40 devices.
Table 4-79. EP1S40 External I/O Timing on Column Pins Using Fast Regional Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX 2.696 0.000 2.506 2.446 2.446 5.015 4.889 4.889
-6 Speed Grade Min
2.907 0.000 2.506 2.446 2.446 5.348 5.216 5.216
-7 Speed Grade Min
3.290 0.000 2.506 2.446 2.446 5.809 5.685 5.685
-8 Speed Grade Unit Min
2.899 0.000 2.698 2.638 2.638 7.286 7.171 7.171
Max
Max
Max
Max
ns ns ns ns ns
Table 4-80. EP1S40 External I/O Timing on Column Pins Using Regional Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 2.413 0.000 2.668 2.608 2.608 1.385 0.000 1.117 1.057 1.057 2.382 2.256 2.256 5.254 5.128 5.128
-6 Speed Grade Min
2.581 0.000 2.668 2.608 2.608 1.376 0.000 1.117 1,057 1,057 2.552 2.420 2.420 5.628 5.496 5.496
-7 Speed Grade Min
2.914 0.000 2.668 2.608 2.608 1.609 0.000 1.117 1.057 1.057 2.504 2.380 2.380 6.132 6.008 6.008
-8 Speed Grade Unit Min
2.938 0.000 2.869 2.809 2.809 1.837 0.000 1.117 1.057 1.057 2.542 2.427 2.427 7.307 7.192 7.192
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
4-48 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-81. EP1S40 External I/O Timing on Column Pins Using Global Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 2.126 0.000 2.856 2.796 2.796 1.466 0.000 1.092 1.032 1.032 2.345 2.219 2.219 5.585 5.459 5.459
-6 Speed Grade Min
2.268 0.000 2.856 2.796 2.796 1.455 0.000 1.092 1.032 1.032 2.510 2.378 2.378 5.987 5.855 5.855
-7 Speed Grade Min
2.558 0.000 2.856 2.796 2.796 1.711 0.000 1.092 1.032 1.032 2.455 2.331 2.331 6.541 6.417 6.417
-8 Speed Grade Unit Min
2.930 0.000 2.847 2.787 2.787 1.906 0.000 1.089 1.029 1.029 2.473 2.358 2.358 7.253 7.138 7.138
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-82. EP1S40 External I/O Timing on Row Pins Using Fast Regional Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX 2.472 0.000 2.631 2.658 2.658 5.258 5.312 5.312
-6 Speed Grade Min
2.685 0.000 2.631 2.658 2.658 5.625 5.681 5.681
-7 Speed Grade Min
3.083 0.000 2.631 2.658 2.658 6.105 6.173 6.173
-8 Speed Grade Unit Min
3.056 0.000 2.745 2.772 2.772 7.324 7.406 7.406
Max
Max
Max
Max
ns ns ns ns ns
Altera Corporation July 2005
4-49 Stratix Device Handbook, Volume 1
Timing Model
Table 4-83. EP1S40 External I/O Timing on Row Pins Using Regional Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 2.349 0.000 2.725 2.752 2.752 1.328 0.000 1.169 1.196 1.196 2.502 2.556 2.556 5.381 5.435 5.435
-6 Speed Grade Min
2.526 0.000 2.725 2.752 2.752 1.322 0.000 1.169 1.196 1.196 2.698 2.754 2.754 5.784 5.840 5.840
-7 Speed Grade Min
2.898 0.000 2.725 2.752 2.752 1.605 0.000 1.169 1.196 1.196 2.650 2.718 2.718 6.290 6.358 6.358
-8 Speed Grade Unit Min
2.952 0.000 2.725 2.936 2.936 1.883 0.000 1.169 1.196 1.196 2.691 2.773 2.773 7.426 7.508 7.508
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-84. EP1S40 External I/O Timing on Row Pins Using Global Clock Networks -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 2.020 0.000 2.912 2.939 2.939 1.370 0.000 1.144 1.171 1.171 2.460 2.514 2.514 5.710 5.764 5.764
-6 Speed Grade Min
2.171 0.000 2.912 2.939 2.939 1.368 0.000 1.144 1.171 1.171 2.652 2.708 2.708 6.139 6.195 6.195
-7 Speed Grade Min
2.491 0.000 2.912 2.939 2.939 1.654 0.000 1.144 1.171 1.171 2.601 2.669 2.669 6.697 6.765 6.765
-8 Speed Grade Unit Min
2.898 0.000 2.931 2.958 2.958 1.881 0.000 1.170 1.197 1.197 2.693 2.775 2.775 7.480 7.562 7.562
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
4-50 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Tables 4-85 through 4-90 show the external timing parameters on column and row pins for EP1S60 devices.
Table 4-85. EP1S60 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX 3.029 0.000 2.446 2.386 2.386 4.871 4.745 4.745
-6 Speed Grade Min
3.277 0.000 2.446 2.386 2.386 5.215 5.083 5.083
-7 Speed Grade Min
3.733 0.000 2.446 2.386 2.386 5.685 5.561 5.561
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
Table 4-86. EP1S60 External I/O Timing on Column Pins Using Regional Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 2.491 0.000 2.767 2.707 2.707 1.233 0.000 1.078 1.018 1.018 2.278 2.152 2.152 5.409 5.283 5.283
-6 Speed Grade Min
2.691 0.000 2.767 2.707 2.707 1.270 0.000 1.078 1.018 1.018 2.395 2.263 2.263 5.801 5.669 5.669
-7 Speed Grade Min
3.060 0.000 2.767 2.707 2.707 1.438 0.000 1.078 1.018 1.018 2.428 2.304 2.304 6.358 6.234 6.234
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Altera Corporation July 2005
4-51 Stratix Device Handbook, Volume 1
Timing Model
Table 4-87. EP1S60 External I/O Timing on Column Pins Using Global Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 2.000 0.000 3.051 2.991 2.991 1.315 0.000 1.029 0.969 0.969 2.196 2.070 2.070 5.900 5.774 5.774
-6 Speed Grade Min
2.152 0.000 3.051 2.991 2.991 1.362 0.000 1.029 0.969 0.969 2.303 2.171 2.171 6.340 6.208 6.208
-7 Speed Grade Min
2.441 0.000 3.051 2.991 2.991 1.543 0.000 1.029 0.969 0.969 2.323 2.199 2.199 6.977 6.853 6.853
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-88. EP1S60 External I/O Timing on Row Pins Using Fast Regional Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX 3.144 0.000 2.643 2.670 2.670 5.275 5.329 5.329
-6 Speed Grade Min
3.393 0.000 2.643 2.670 2.670 5.654 5.710 5.710
-7 Speed Grade Min
3.867 0.000 2.643 2.670 2.670 6.140 6.208 6.208
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
4-52 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-89. EP1S60 External I/O Timing on Row Pins Using Regional Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 2.775 0.000 2.867 2.894 2.894 1.523 0.000 1.174 1.201 1.201 2.507 2.561 2.561 5.644 5.698 5.698
-6 Speed Grade Min
2.990 0.000 2.867 2.894 2.894 1.577 0.000 1.174 1.201 1.201 2.643 2.699 2.699 6.057 6.113 6.113
-7 Speed Grade Min
3.407 0.000 2.867 2.894 2.894 1.791 0.000 1.174 1.201 1.201 2.664 2.732 2.732 6.600 6.668 6.668
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-90. EP1S60 External I/O Timing on Row Pins Using Global Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL
(1)
-6 Speed Grade Min
2.393 0.000
-7 Speed Grade Min
2.721 0.000
-8 Speed Grade Unit Min
NA NA
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
2.232 0.000 3.182 3.209 3.209 1.651 0.000 1.154 1.181 1.181 2.469 2.523 2.523 6.187 6.241 6.241
3.182 3.209 3.209 1.612 0.000 1.154 1.181 1.181
6.654 6.710 6.710
3.182 3.209 3.209 1.833 0.000
7.286 7.354 7.354
NA NA NA NA NA
2.608 2.664 2.664
1.154 1.181 1.181
2.622 2.690 2.690
NA NA NA
Note to Tables 4-85 to 4-90:
Only EP1S25, EP1S30, and EP1S40 devices have the -8 speed grade.
Altera Corporation July 2005
4-53 Stratix Device Handbook, Volume 1
Timing Model
Tables 4-91 through 4-96 show the external timing parameters on column and row pins for EP1S80 devices.
Table 4-91. EP1S80 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX 2.328 0.000 2.422 2.362 2.362 4.830 4.704 4.704
-6 Speed Grade Min
2.528 0.000 2.422 2.362 2.362 5.169 5.037 5.037
-7 Speed Grade Min
2.900 0.000 2.422 2.362 2.362 5.633 5.509 5.509
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
Table 4-92. EP1S80 External I/O Timing on Column Pins Using Regional Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 1.760 0.000 2.761 2.701 2.701 0.462 0.000 1.661 1.601 1.601 2.849 2.723 2.723 5.398 5.272 5.272
-6 Speed Grade Min
1.912 0.000 2.761 2.701 2.701 0.606 0.000 1.661 1.601 1.601 2.859 2.727 2.727 5.785 5.653 5.653
-7 Speed Grade Min
2.194 0.000 2.761 2.701 2.701 0.785 0.000 1.661 1.601 1.601 2.881 2.757 2.757 6.339 6.215 6.215
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
4-54 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-93. EP1S80 External I/O Timing on Column Pins Using Global Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 0.884 0.000 3.267 3.207 3.207 0.506 0.000 1.635 1.575 1.575 2.805 2.679 2.679 6.274 6.148 6.148
-6 Speed Grade Min
0.976 0.000 3.267 3.207 3.207 0.656 0.000 1.635 1.575 1.575 2.809 2.677 2.677 6.721 6.589 6.589
-7 Speed Grade Min
1.118 0.000 3.267 3.207 3.207 0.838 0.000 1.635 1.575 1.575 2.828 2.704 2.704 7.415 7.291 7.291
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-94. EP1S80 External I/O Timing on Row Pins Using Fast Regional Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX 2.792 0.000 2.619 2.646 2.646 5.235 5.289 5.289
-6 Speed Grade Min
2.993 0.000 2.619 2.646 2.646 5.609 5.665 5.665
-7 Speed Grade Min
3.386 0.000 2.619 2.646 2.646 6.086 6.154 6.154
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns
Altera Corporation July 2005
4-55 Stratix Device Handbook, Volume 1
Timing Model
Table 4-95. EP1S80 External I/O Timing on Row Pins Using Regional Clock Networks Note (1) -5 Speed Grade Parameter Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL 2.295 0.000 2.917 2.944 2.944 1.011 0.000 1.808 1.835 1.835 3.169 3.223 3.223 5.732 5.786 5.786
-6 Speed Grade Min
2.454 0.000 2.917 2.944 2.944 1.161 0.000 1.808 1.835 1.835 3.209 3.265 3.265 6.148 6.204 6.204
-7 Speed Grade Min
2.767 0.000 2.917 2.944 2.944 1.372 0.000 1.808 1.835 1.835 3.233 3.301 3.301 6.705 6.773 6.773
-8 Speed Grade Unit Min
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
Max
Max
Max
Max
ns ns ns ns ns ns ns ns ns ns
Table 4-96. EP1S80 External I/O Timing on Rows Using Pin Global Clock Networks Note (1) -5 Speed Grade Symbol Min
tINSU tINH tOUTCO tXZ tZX tINSUPLL tINHPLL tOUTCOPLL tXZPLL tZXPLL
(1)
-6 Speed Grade Min
1.451 0.000
-7 Speed Grade Min
1.613 0.000
-8 Speed Grade Unit Min
NA NA
Max
Max
Max
Max
ns ns NA NA NA ns ns ns ns ns NA NA NA ns ns ns
1.362 0.000 3.457 3.484 3.484 o.994 0.000 1.821 1.848 1.848 3.186 3.240 3.240 6.665 6.719 6.719
3.457 3.484 3.484 1.143 0.000 1.821 1.848 1.848
7.151 7.207 7.207
3.457 3.484 3.484 1.351 0.000
7.859 7.927 7.927
NA NA NA NA NA
3.227 3.283 3.283
1.821 1.848 1.848
3.254 3.322 3.322
NA NA NA
Note to Tables 4-91 to 4-96:
Only EP1S25, EP1S30, and EP1S40 devices have the -8 speed grade.
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Altera Corporation July 2005
DC & Switching Characteristics
Definition of I/O Skew
I/O skew is defined as the absolute value of the worst-case difference in clock-to-out times (tCO) between any two output registers fed by a common clock source. I/O bank skew is made up of the following components:

Clock network skews: This is the difference between the arrival times of the clock at the clock input port of the two IOE registers. Package skews: This is the package trace length differences between (I/O pad A to I/O pin A) and (I/O pad B to I/O pin B).
Figure 4-5 shows an example of two IOE registers located in the same bank, being fed by a common clock source. The clock can come from an input pin or from a PLL output. Figure 4-5. I/O Skew within an I/O Bank
I/O Bank I/O Pin A
Common Source of GCLK I/O Pin B
Fast Edge I/O Pin A
Slow Edge I/O Pin B I/O Skew I/O Skew
Altera Corporation July 2005
4-57 Stratix Device Handbook, Volume 1
Timing Model
Figure 4-6 shows the case where four IOE registers are located in two different I/O banks. Figure 4-6. I/O Skew Across Two I/O Banks
I/O Bank I/O Pin A
I/O Pin B
Common Source of GCLK
I/O Pin C
I/O Pin D I/O Bank
I/O Pin Skew across two Banks
I/O Pin A I/O Pin B I/O Pin C I/O Pin D
Table 4-97 defines the timing parameters used to define the timing for horizontal I/O pins (side banks 1, 2, 5, 6) and vertical I/O pins (top and bottom banks 3, 4, 7, 8). The timing parameters define the skew within an I/O bank, across two neighboring I/O banks on the same side of the device, across all horizontal I/O banks, across all vertical I/O banks, and the skew for the overall device.
Table 4-97. Output Pin Timing Skew Definitions (Part 1 of 2) Symbol
tSB_HIO tSB_VIO tSS_HIO tSS_VIO
Definition
Row I/O (HIO) within one I/O bank (1) Column I/O (VIO) within one I/O bank (1) Row I/O (HIO) same side of the device, across two banks (2) Column I/O (VIO) same side of the device, across two banks (2)
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Altera Corporation July 2005
DC & Switching Characteristics
Table 4-97. Output Pin Timing Skew Definitions (Part 2 of 2) Symbol
tLR_HIO tTB_VIO tOVERALL Notes to Table 4-97:
(1) (2) See Figure 4-5 on page 4-57. See Figure 4-6 on page 4-58.
Definition
Across all HIO banks (1, 2, 5, 6); across four similar type I/O banks Across all VIO banks (3, 4, 7, 8); across four similar type I/O banks Output timing skew for all I/O pins on the device.
Table 4-98 shows the I/O skews when using the same global or regional clock to feed IOE registers in I/O banks around each device. These values can be used for calculating the timing budget on the output (write) side of a memory interface. These values already factor in the package skew.
Table 4-98. Output Skew for Stratix by Device Density Skew (ps) (1) Symbol EP1S10 to EP1S30
tSB_HIO tSB_VIO tSS_HIO tSS_VIO tLR_HIO tTB_VIO tOVERALL Note to Table 4-98:
(1) The skew numbers in Table 4-98 account for worst case package skews.
EP1S40
290 290 460 520 490 580 630
EP1S60 & EP1S80
500 500 600 630 600 670 880
90 160 90 180 150 190 430
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4-59 Stratix Device Handbook, Volume 1
Timing Model
Skew on Input Pins
Table 4-99 shows the package skews that were considered to get the worst case I/O skew value. You can use these values, for example, when calculating the timing budget on the input (read) side of a memory interface.
Table 4-99. Package Skew on Input Pins Package Parameter
Pins in the same I/O bank Pins in top/bottom (vertical I/O) banks Pins in left/right side (horizontal I/O) banks Pins across the entire device
Worst-Case Skew (ps)
50 50 50 100
PLL Counter & Clock Network Skews
Table 4-100 shows the clock skews between different clock outputs from the Stratix device PLL.
Table 4-100. PLL Counter & Clock Network Skews Parameter
Clock skew between two external clock outputs driven by the same counter Clock skew between two external clock outputs driven by the different counters with the same settings Dual-purpose PLL dedicated clock output used as I/O pin vs. regular I/O pin Clock skew between any two outputs of the PLL that drive global clock networks Note to Table 4-100:
(1) The Quartus II software models 270 ps of delay on the PLL dedicated clock output (PLL6_OUT[3..0]p/n and PLL5_OUT[3..0]p/n) pins both when used as clocks and when used as I/O pins.
Worst-Case Skew (ps)
100 150 270 (1) 150
I/O Timing Measurement Methodology
Different I/O standards require different baseline loading techniques for reporting timing delays. Altera characterizes timing delays with the required termination and loading for each I/O standard. The timing information is specified from the input clock pin up to the output pin of
4-60 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
the FPGA device. The Quartus II software calculates the I/O timing for each I/O standard with a default baseline loading as specified by the I/O standard. Altera measures clock-to-output delays (tCO) at worst-case process, minimum voltage, and maximum temperature (PVT) for the 3.3-V LVTTL I/O standard with 24 mA (default case) current drive strength setting and fast slew rate setting. I/O adder delays are measured to calculate the tCO change at worst-case PVT across all I/O standards and current drive strength settings with the default loading shown in Table 4-101 on page 4-62. Timing derating data for additional loading is taken for tCO across worst-case PVT for all I/O standards and drive strength settings. These three pieces of data are used to predict the timing at the output pin. tCO at pin = tOUTCO max for 3.3-V 24 mA LVTTL + I/O Adder + Output Delay Adder for Loading Simulation using IBIS models is required to determine the delays on the PCB traces in addition to the output pin delay timing reported by the Quartus II software and the timing model in the device handbook. 1. Simulate the output driver of choice into the generalized test setup using values from Table 4-101 on page 4-62. Record the time to VMEAS. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS input buffer model or an equivalent capacitance value to represent the load. Record the time to VMEAS. Compare the results of steps 2 and 4. The increase or decrease in delay should be added to or subtracted from the I/O Standard Output Adder delays to yield the actual worst-case propagation delay (clock-to-input) of the PCB trace.
2. 3.
4. 5.
The Quartus II software reports maximum timing with the conditions shown in Table 4-101 on page 4-62 using the proceeding equation. Figure 4-7 on page 4-62 shows the model of the circuit that is represented by the Quartus II output timing.
Altera Corporation July 2005
4-61 Stratix Device Handbook, Volume 1
Timing Model
Figure 4-7. Output Delay Timing Reporting Setup Modeled by Quartus II
VCCIO Single-Ended Outputs VCCIO RUP Output Buffer OUTPUT VMEAS RDN CL RS VTT RT
GND
GND
GND
Notes to Figure 4-7:
(1) Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay need to be accounted for with IBIS model simulations. VCCINT is 1.42-V unless otherwise specified.
(2)
Table 4-101. Reporting Methodology For Maximum Timing For Single-Ended Output Pins (Part 1 of 2) Notes (1), (2), (3) Loading and Termination I/O Standard RUP
3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL 3.3-V LVCMOS 2.5-V LVCMOS 1.8-V LVCMOS 1.5-V LVCMOS 3.3-V GTL 2.5-V GTL 3.3-V GTL+ 2.5-V GTL+ 3.3-V SSTL-3 Class II - - - - - - - - - - - - -
Measurement Point VTT (V)
2.95 2.37 1.65 1.40 2.95 2.37 1.65 1.40 1.14 1.14 1.35 1.35 1.25
RDN
- - - - - - - - - - - - -
RS
0 0 0 0 0 0 0 0 0 0 0 0 25
RT
- - - - - - - - 25 25 25 25 25
VCCIO (V)
2.950 2.370 1.650 1.400 2.950 2.370 1.650 1.400 2.950 2.370 2.950 2.370 2.950
CL (pF)
10 10 10 10 10 10 10 10 30 30 30 30 30
VMEAS
1.500 1.200 0.880 0.750 1.500 1.200 0.880 0.750 0.740 0.740 0.880 0.880 1.250
4-62 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-101. Reporting Methodology For Maximum Timing For Single-Ended Output Pins (Part 2 of 2) Notes (1), (2), (3) Loading and Termination I/O Standard RUP
3.3-V SSTL-3 Class I 2.5-V SSTL-2 Class II 2.5-V SSTL-2 Class I 1.8-V SSTL-18 Class II 1.8-V SSTL-18 Class I 1.5-V HSTL Class II 1.5-V HSTL Class I 1.8-V HSTL Class II 1.8-V HSTL Class I 3.3-V PCI (4) 3.3-V PCI-X 1.0 (4) 3.3-V Compact PCI (4) 3.3-V AGP 1X (4) 3.3-V CTT Notes to Table 4-101:
(1) (2) (3) (4) Input measurement point at internal node is 0.5 x VCCINT. Output measuring point for data is VMEAS. Input stimulus edge rate is 0 to VCCINT in 0.5 ns (internal signal) from the driver preceding the IO buffer. The first value is for output rising edge and the second value is for output falling edge. The hyphen (-) indicates infinite resistance or disconnection.
Measurement Point VTT (V)
1.250 1.110 1.110 0.760 0.760 0.700 0.700 0.700 0.700 2.950 2.950 2.950 2.950 1.350
RDN
- - - - - - - - - 25/- 25/- 25/- 25/- -
RS
25 25 25 25 25 0 0 0 0 0 0 0 0 25
RT
50 25 50 25 50 25 50 25 50 - - - - 50
VCCIO (V)
2.950 2.370 2.370 1.650 1.650 1.400 1.400 1.650 1.650 2.950 2.950 2.950 2.950 2.050
CL (pF)
30 30 30 30 30 20 20 20 20 10 10 10 10 30
VMEAS
1.250 1.110 1.110 0.760 0.760 0.680 0.680 0.880 0.880 0.841/1.814 0.841/1.814 0.841/1.814 0.841/1.814 1.350
- - - - - - - - - -/25 -/25 -/25 -/25 -
Altera Corporation July 2005
4-63 Stratix Device Handbook, Volume 1
Timing Model
Table 4-102 shows the reporting methodology used by the Quartus II software for minimum timing information for output pins.
Table 4-102. Reporting Methodology For Minimum Timing For Single-Ended Output Pins (Part 1 of 2) Notes (1), (2), (3) Loading and Termination I/O Standard RUP
3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL 3.3-V LVCMOS 2.5-V LVCMOS 1.8-V LVCMOS 1.5-V LVCMOS 3.3-V GTL 2.5-V GTL 3.3-V GTL+ 2.5-V GTL+ 3.3-V SSTL-3 Class II 3.3-V SSTL-3 Class I 2.5-V SSTL-2 Class II 2.5-V SSTL-2 Class I 1.8-V SSTL-18 Class II 1.8-V SSTL-18 Class I 1.5-V HSTL Class II 1.5-V HSTL Class I 1.8-V HSTL Class II 1.8-V HSTL Class I 3.3-V PCI (4) 3.3-V PCI-X 1.0 (4) 3.3-V Compact PCI (4) 3.3-V AGP 1x (4) - - - - - - - - - - - - - - - - - - - - - - -/25 -/25 -/25 -/25
Measurement Point VTT (V)
3.600 2.630 1.950 1.600 3.600 2.630 1.950 1.600 1.260 1.260 1.650 1.650 1.750 1.750 1.390 1.390 1.040 1.040 0.800 0.800 0.900 0.900 1.950 1.950 3.600 3.600
RDN
- - - - - - - - - - - - - - - - - - - - - - 25/- 25/- 25/- 25/-
RS
0 0 0 0 0 0 0 0 0 0 0 0 25 25 25 25 25 25 0 0 0 0 0 0 0 0
RT
- - - - - - - - 25 25 25 25 25 50 25 50 25 50 25 50 25 50 - - - -
VCCIO (V)
3.600 2.630 1.950 1.600 3.600 2.630 1.950 1.600 3.600 2.630 3.600 2.630 3.600 3.600 2.630 2.630 1.950 1.950 1.600 1.600 1.950 1.950 3.600 3.600 3.600 3.600
CL (pF)
10 10 10 10 10 10 10 10 30 30 30 30 30 30 30 30 30 30 20 20 20 20 10 10 10 10
VMEAS
1.800 1.200 0.880 0.750 1.800 1.200 0.880 0.750 0.860 0.860 1.120 1.120 1.750 1.750 1.390 1.390 1.040 1.040 0.900 0.900 1.000 1.000 1.026/2.214 1.026/2.214 1.026/2.214 1.026/2.214
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Altera Corporation July 2005
DC & Switching Characteristics
Table 4-102. Reporting Methodology For Minimum Timing For Single-Ended Output Pins (Part 2 of 2) Notes (1), (2), (3) Loading and Termination I/O Standard RUP
3.3-V CTT Notes to Table 4-102:
(1) (2) (3) (4) Input measurement point at internal node is 0.5 x VCCINT. Output measuring point for data is VMEAS. When two values are given, the first is the measurement point on the rising edge and the other is for the falling edge. Input stimulus edge rate is 0 to VCCINT in 0.5 ns (internal signal) from the driver preceding the I/O buffer. The first value is for the output rising edge and the second value is for the output falling edge. The hyphen (-) indicates infinite resistance or disconnection.
Measurement Point VTT (V)
1.650
RDN
-
RS
25
RT
50
VCCIO (V)
3.600
CL (pF)
30
VMEAS
1.650
-
Figure 4-8 shows the measurement setup for output disable and output enable timing. The TCHZ stands for clock to high Z time delay and is the same as TXZ. The TCLZ stands for clock to low Z (driving) time delay and is the same as TZX. Figure 4-8. Measurement Setup for TXZ and TZX
CLK T CHZ 200mV
VT =1.5V
OUT
R =50 200mV T CLZ 200mV C TOTAL =10pF
OUT
200mV
Altera Corporation July 2005
4-65 Stratix Device Handbook, Volume 1
Timing Model
External I/O Delay Parameters
External I/O delay timing parameters for I/O standard input and output adders and programmable input and output delays are specified by speed grade independent of device density. All of the timing parameters in this section apply to both flip-chip and wire-bond packages. Tables 4-103 and 4-104 show the input adder delays associated with column and row I/O pins. If an I/O standard is selected other than 3.3-V LVTTL or LVCMOS, add the selected delay to the external tINSU and tINSUPLL I/O parameters shown in Tables 4-54 through 4-96.
Table 4-103. Stratix I/O Standard Column Pin Input Delay Adders -5 Speed Grade Parameter Min
LVCMOS 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL GTL GTL+ 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II
-6 Speed Grade Min Max
0 0 19 232 369 -48 -79 0 0 0 0 0 126 -171 -171 -213 -213 81 81 -80 -80 -55 -55
-7 Speed Grade Min Max
0 0 22 266 425 -55 -91 0 0 0 0 0 144 -196 -196 -244 -244 94 94 -92 -92 -63 -63
-8 Speed Grade Unit Min Max
0 0 26 313 500 -64 -107 0 0 0 0 0 170 -231 -231 -287 -287 110 110 -108 -108 -74 -74 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
0 0 19 221 352 -45 -75 0 0 0 0 0 120 -162 -162 -202 -202 78 78 -76 -76 -52 -52
4-66 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-104. Stratix I/O Standard Row Pin Input Delay Adders -5 Speed Grade Parameter Min
LVCMOS 3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL GTL+ CTT SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.8-V HSTL Class I LVDS LVPECL 3.3-V PCML HyperTransport
-6 Speed Grade Min Max
0 0 22 190 315 -160 -177 -203 -203 -276 -276 -111 0 -159 -133 -157 -157 -69 -81
-7 Speed Grade Min Max
0 0 25 218 362 -184 -203 -234 -234 -317 -317 -127 0 -183 -153 -180 -180 -79 -93
-8 Speed Grade Unit Min Max
0 0 29 257 426 -216 -239 -275 -275 -373 -373 -150 0 -215 -179 -212 -212 -93 -110 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
0 0 21 181 300 -152 -168 -193 -193 -262 -262 -105 0 -151 -126 -149 -149 -65 77
Altera Corporation July 2005
4-67 Stratix Device Handbook, Volume 1
Timing Model
Tables 4-105 through 4-108 show the output adder delays associated with column and row I/O pins for both fast and slow slew rates. If an I/O standard is selected other than 3.3-V LVTTL 4mA or LVCMOS 2 mA with a fast slew rate, add the selected delay to the external tOUTCO, tOUTCOPLL, tXZ, tZX, tXZPLL, and tZXPLL I/O parameters shown in Table 4-55 on page 4-36 through Table 4-96 on page 4-56.
Table 4-105. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2) -5 Speed Grade Parameter Min
LVCMOS 2 mA 4 mA 8 mA 12 mA 24 mA 3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 24 mA 2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA 1.8-V LVTTL 2 mA 8 mA 12 mA 1.5-V LVTTL 2 mA 4 mA 8 mA GTL GTL+ 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x
-6 Speed Grade Min Max
1,990 1,004 198 0 -165 1,990 1,414 668 589 0 2,643 875 529 203 1,369 1,008 1,008 7,014 3,439 1,668 17 9 52 52 52 52 1,990
-7 Speed Grade Min Max
1,990 1,004 198 0 -165 1,990 1,414 668 589 0 2,643 875 529 203 1,369 1,008 1,008 7,014 3,439 1,668 17 9 52 52 52 52 1,990
-8 Speed Grade Unit Min Max
1,990 1,004 198 0 -165 1,990 1,414 668 589 0 2,643 875 529 203 1,369 1,008 1,008 7,014 3,439 1,668 17 9 52 52 52 52 1,990 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
1,895 956 189 0 -157 1,895 1,347 636 561 0 2,517 834 504 194 1,304 960 960 6,680 3,275 1,589 16 9 50 50 50 50 1,895
4-68 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-105. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 2 of 2) -5 Speed Grade Parameter Min
CTT SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II
-6 Speed Grade Min Max
1,021 755 153 712 234 1,083 469 693 564 319 242
-7 Speed Grade Min Max
1,021 755 153 712 234 1,083 469 693 564 319 242
-8 Speed Grade Unit Min Max
1,021 755 153 712 234 1,083 469 693 564 319 242 ps ps ps ps ps ps ps ps ps ps ps
Max
973 719 146 678 223 1,032 447 660 537 304 231
Table 4-106. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins -5 Speed Grade Parameter Min
LVCMOS 2 mA 4 mA 8 mA 12 mA 3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 24 mA 2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA 1.8-V LVTTL 2 mA 8 mA 12 mA
(Part 1 of 2) Unit
-6 Speed Grade Min Max
1,594 783 100 0 1,594 1,090 547 434 0 2,133 734 392 173 3,899 1,107 871
-7 Speed Grade Min Max
1,594 783 100 0 1,594 1,090 547 434 0 2,133 734 392 173 3,899 1,107 871
-8 Speed Grade Min Max
1,594 783 100 0 1,594 1,090 547 434 0 2,133 734 392 173 3,899 1,107 871 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
1,518 746 96 0 1,518 1,038 521 414 0 2,032 699 374 165 3,714 1,055 830
Altera Corporation July 2005
4-69 Stratix Device Handbook, Volume 1
Timing Model
Table 4-106. Stratix I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins -5 Speed Grade Parameter Min
1.5-V LVTTL 2 mA 4 mA 8 mA GTL+ CTT SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I 1.5-V HSTL Class I 1.8-V HSTL Class I LVDS LVPECL PCML HyperTransport technology Note to Table 4-103 through 4-106:
(1) These parameters are only available on row I/O pins.
(Part 2 of 2) Unit
-6 Speed Grade Min Max
5,733 2,824 1,468 6 887 670 151 634 221 1,002 769 390 -206 -156 -155 -98
-7 Speed Grade Min Max
5,733 2,824 1,468 6 887 670 151 634 221 1,002 769 390 -206 -156 -155 -98
-8 Speed Grade Min Max
5,733 2,824 1,468 6 887 670 151 634 221 1,002 769 390 -206 -156 -155 -98 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
5,460 2,690 1,398 6 845 638 144 604 211 955 733 372 -196 -148 -147 -93
Table 4-107. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 1 of 2) -5 Speed Grade Parameter Min
LVCMOS 2 mA 4 mA 8 mA 12 mA 24 mA
-6 Speed Grade Min Max
1,913 718 245 1 -638
-7 Speed Grade Min Max
1,913 718 245 1 -638
-8 Speed Grade Unit Min Max
1,913 718 245 1 -638 ps ps ps ps ps
Max
1,822 684 233 1 -608
4-70 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-107. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part 2 of 2) -5 Speed Grade Parameter Min
3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 24 mA 2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA 1.8-V LVTTL 2 mA 8 mA 12 mA 1.5-V LVTTL 2 mA 4 mA 8 mA GTL GTL+ 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II
-6 Speed Grade Min Max
1,913 1,665 720 662 0 3,071 1,571 984 1,053 7,456 3,801 3,265 11,488 7,803 6,290 -1,007 -460 693 693 693 693 303 663 316 -377 549 -51 2,431 759 1,771 1,150 629 102
-7 Speed Grade Min Max
1,913 1,665 720 662 0 3,071 1,571 984 1,053 7,456 3,801 3,265 11,488 7,803 6,290 -1,007 -460 693 693 693 693 303 663 316 -377 549 -51 2,431 759 1,771 1,150 678 102
-8 Speed Grade Unit Min Max
1,913 1,665 720 662 0 3,071 1,571 984 1,053 7,456 3,801 3,265 11,488 7,803 6,290 -1,007 -460 693 693 693 693 303 663 316 -377 549 -51 2,431 759 1,771 1,150 744 102 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
1,822 1,586 686 630 0 2,925 1,496 937 1,003 7,101 3,620 3,109 10,941 7,431 5,990 -959 -438 660 660 660 660 288 631 301 -359 523 -49 2,315 723 1,687 1,095 599 87
Altera Corporation July 2005
4-71 Stratix Device Handbook, Volume 1
Timing Model
Table 4-108. Stratix I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins -5 Speed Grade I/O Standard Min
LVCMOS 2 mA 4 mA 8 mA 12 mA 3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 2.5-V LVTTL 2 mA 8 mA 12 mA 16 mA 1.8-V LVTTL 2 mA 8 mA 12 mA 1.5-V LVTTL 2 mA 4 mA 8 mA GTL+ CTT SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I 1.5-V HSTL Class I 1.8-V HSTL Class I
-6 Speed Grade Min Max
1,650 624 218 0 1,650 1,463 626 590 2,690 1,410 907 992 6,621 3,538 3,079 10,247 7,172 5,984 -350 621 280 -363 505 -61 2,317 2,064 1,268
-7 Speed Grade Min Max
1,650 624 218 0 1,650 1,463 626 590 2,690 1,410 907 992 6,621 3,538 3,079 10,247 7,172 5,984 -350 621 280 -363 505 -61 2,317 2,064` 1,460
-8 Speed Grade Unit Min Max
1,650 624 218 0 1,650 1,463 626 590 2,690 1,410 907 992 6,621 3,538 3,079 10,247 7,172 5,984 -350 621 280 -363 505 -61 2,317 2,064 1,720 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Max
1,571 594 208 0 1,571 1,393 596 562 2,562 1,343 864 945 6,306 3,369 2,932 9,759 6,830 5,699 -333 591 267 -346 481 -58 2,207 1,966 1,208
4-72 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Tables 4-109 and 4-110 show the adder delays for the column and row IOE programmable delays. These delays are controlled with the Quartus II software logic options listed in the Parameter column.
Table 4-109. Stratix IOE Programmable Delays on Column Pins Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter
Decrease input delay to internal cells
Setting Min
Off Small Medium Large On
Unit Max
3,970 3,390 2,810 224 224 3,900 0 1,240 0 0 397 0 338 0 540 1,016 1,016 0 540 1,016 1,016 0 540 1,016 1,016 0 2,199
Min
Max
4,367 3,729 3,091 235 235 4,290 0 1,364 0 0 417 0 372 0 594 1,118 1,118 0 594 1,118 1,118 0 594 1,118 1,118 0 2,309
Min
Max
5,022 4,288 3,554 270 270 4,933 0 1,568 0 0 417 0 427 0 683 1,285 1,285 0 683 1,285 1,285 0 683 1,285 1,285 0 2,309
Min
Max
5,908 5,045 4,181 318 318 5,804 0 1,845 0 0 417 0 503 0 804 1,512 1,512 0 804 1,512 1,512 0 804 1,512 1,512 0 2,309 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Decrease input delay to input register Decrease input delay to output register Increase delay to output pin Increase delay to output enable pin Increase output clock enable delay
Off On Off On Off On Off On Off Small Large On
Increase input clock enable delay
Off Small Large On
Increase output enable clock enable delay
Off Small Large On
Increase tZX delay to output pin
Off On
Altera Corporation July 2005
4-73 Stratix Device Handbook, Volume 1
Timing Model
Table 4-110. Stratix IOE Programmable Delays on Row Pins Note (1) -5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade Parameter
Decrease input delay to internal cells
Setting Min
Off Small Medium Large On
Unit Max
3,970 3,390 2,810 173 173 3,900 0 1,240 0 0 397 0 348 0 180 260 260 0 180 260 260 0 540 1,016 1,016 0 1,993
Min
Max
4,367 3,729 3,091 181 181 4,290 0 1,364 0 0 417 0 383 0 198 286 286 0 198 286 286 0 594 1,118 1,118 0 2,092
Min
Max
5,022 4,288 3,554 208 208 4,933 0 1,568 0 0 417 0 441 0 227 328 328 0 227 328 328 0 683 1,285 1,285 0 2,092
Min
Max
5,908 5,045 4,181 245 245 5,804 0 1,845 0 0 417 0 518 0 267 386 386 0 267 386 386 0 804 1,512 1,512 0 2,092 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Decrease input delay to input register Decrease input delay to output register Increase delay to output pin Increase delay to output enable pin Increase output clock enable delay
Off On Off On Off On Off On Off Small Large On
Increase input clock enable delay
Off Small Large On
Increase output enable clock enable delay
Off Small Large On
Increase tZX delay to output pin
Off On
Note to Table 4-109 and Table 4-110:
(1) The delay chain delays vary for different device densities. These timing values only apply to EP1S30 and EP1S40 devices. Reference the timing information reported by the Quartus II software for other devices.
4-74 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
The scaling factors for column output pin timing in Tables 4-111 to 4-113 are shown in units of time per pF unit of capacitance (ps/pF). Add this delay to the tCO or combinatorial timing path for output or bidirectional pins in addition to the I/O adder delays shown in Tables 4-103 through 4-108 and the IOE programmable delays in Tables 4-109 and 4-110.
Table 4-111. Output Delay Adder for Loading on LVTTL/LVCMOS Output Buffers Note (1) Conditions Parameter Value
24mA 16mA
Output Pin Adder Delay (ps/pF) 3.3-V LVTTL
15 25 30 50 60 -
2.5-V LVTTL
- 18 25 35 - 75
1.8-V LVTTL
- - 25 40 - 120
1.5-V LVTTL
- - 35 80 160
LVCMOS
8 - 15 20 30 60
Drive Strength
12mA 8mA 4mA 2mA
Note to Table 4-111:
(1) The timing information in this table is preliminary.
Table 4-112. Output Delay Adder for Loading on SSTL/HSTL Output Buffers Conditions SSTL-3
Class I Class II Note to Table 4-112:
(1) The timing information in this table is preliminary.
Note (1)
Output Pin Adder Delay (ps/pF) SSTL-2
25 20
SSTL-1.8
25 25
1.5-V HSTL
25 20
25 25
Table 4-113. Output Delay Adder for Loading on GTL+/GTL/CTT/PCI Output Buffers Conditions Parameter
VCCIO Voltage Level Note to Table 4-113:
(1) The timing information in this table is preliminary.
Note (1)
Output Pin Adder Delay (ps/pF) Value
3.3V 2.5V
GTL+
18 15
GTL
18 18
CTT
25 -
PCI
20 -
AGP
20 -
Altera Corporation July 2005
4-75 Stratix Device Handbook, Volume 1
Timing Model
Maximum Input & Output Clock Rates
Tables 4-114 through 4-119 show the maximum input clock rate for column and row pins in Stratix devices.
Table 4-114. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12] Pins in Flip-Chip Packages (Part 1 of 2) I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential 1.5-V HSTL C1 LVPECL (1) PCML (1)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
422 422 422 422 422 300 300 400 400 400 400 400 400 400 400 400 400 422 422 422 422 422 300 400 645 300 422 422 422 422 422 250 250 350 350 350 350 350 350 350 350 350 350 422 422 422 422 422 250 350 645 275 390 390 390 390 390 200 200 300 300 300 300 300 300 300 300 300 300 390 390 390 390 390 200 300 622 275 390 390 390 390 390 200 200 300 300 300 300 300 300 300 300 300 300 390 390 390 390 390 200 300 622 275
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
4-76 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-114. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12] Pins in Flip-Chip Packages (Part 2 of 2) I/O Standard
LVDS (1) HyperTransport technology (1)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
645 500 645 500 622 450 622 450
Unit
MHz MHz
Table 4-115. Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins & FPLL[10..7]CLK Pins in Flip-Chip Packages I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL+ SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.8-V HSTL Class I CTT Differential 1.5-V HSTL C1 LVPECL (1) PCML (1) LVDS (1) HyperTransport technology (1)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
422 422 422 422 422 300 400 400 400 400 400 400 400 400 300 400 717 400 717 717 422 422 422 422 422 250 350 350 350 350 350 350 350 350 250 350 717 375 717 717 390 390 390 390 390 200 300 300 300 300 300 300 300 300 200 300 640 350 640 640 390 390 390 390 390 200 300 300 300 300 300 300 300 300 200 300 640 350 640 640
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Altera Corporation July 2005
4-77 Stratix Device Handbook, Volume 1
Timing Model
Table 4-116. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in Flip-Chip Packages I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL+ SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.8-V HSTL Class I CTT Differential 1.5-V HSTL C1 LVPECL (1) PCML (1) LVDS (1) HyperTransport technology (1)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
422 422 422 422 422 300 400 400 400 400 400 400 400 400 300 400 645 300 645 500 422 422 422 422 422 250 350 350 350 350 350 350 350 350 250 350 645 275 645 500 390 390 390 390 390 200 300 300 300 300 300 300 300 300 200 300 640 275 640 450 390 390 390 390 390 200 300 300 300 300 300 300 300 300 200 300 640 275 640 450
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Table 4-117. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12] Pins in Wire-Bond Packages (Part 1 of 2) I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL
-6 Speed -7 Speed -8 Speed Grade Grade Grade
422 422 422 422 422 250 390 390 390 390 390 200 390 390 390 390 390 200
Unit
MHz MHz MHz MHz MHz MHz
4-78 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-117. Stratix Maximum Input Clock Rate for CLK[7..4] & CLK[15..12] Pins in Wire-Bond Packages (Part 2 of 2) I/O Standard
GTL+ SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential 1.5-V HSTL C1 LVPECL (1) PCML (1) LVDS (1) HyperTransport technology (1)
-6 Speed -7 Speed -8 Speed Grade Grade Grade
250 300 300 300 300 300 300 300 300 300 300 422 422 422 422 422 250 300 422 215 422 422 200 250 250 250 250 250 250 180 180 180 180 390 390 390 390 390 180 180 400 200 400 400 200 250 250 250 250 250 250 180 180 180 180 390 390 390 390 390 180 180 400 200 400 400
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Table 4-118. Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins & FPLL[10..7]CLK Pins in Wire-Bond Packages (Part 1 of 2) I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V
-6 Speed -7 Speed -8 Speed Grade Grade Grade
422 422 422 422 390 390 390 390 390 390 390 390
Unit
MHz MHz MHz MHz
Altera Corporation July 2005
4-79 Stratix Device Handbook, Volume 1
Timing Model
Table 4-118. Stratix Maximum Input Clock Rate for CLK[0, 2, 9, 11] Pins & FPLL[10..7]CLK Pins in Wire-Bond Packages (Part 2 of 2) I/O Standard
LVCMOS GTL+ SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.8-V HSTL Class I CTT Differential 1.5-V HSTL C1 LVPECL (1) PCML (1) LVDS (1) HyperTransport technology (1)
-6 Speed -7 Speed -8 Speed Grade Grade Grade
422 250 350 350 350 350 350 350 350 350 250 350 717 375 717 717 390 200 300 300 300 300 300 300 300 300 200 300 640 350 640 640 390 200 300 300 300 300 300 300 300 300 200 300 640 350 640 640
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Table 4-119. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in Wire-Bond Packages (Part 1 of 2) I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL+ SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II
-6 Speed -7 Speed -8 Speed Grade Grade Grade
422 422 422 422 422 250 350 350 350 350 390 390 390 390 390 200 300 300 300 300 390 390 390 390 390 200 300 300 300 300
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
4-80 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-119. Stratix Maximum Input Clock Rate for CLK[1, 3, 8, 10] Pins in Wire-Bond Packages (Part 2 of 2) I/O Standard
SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.8-V HSTL Class I CTT Differential 1.5-V HSTL C1 LVPECL (1) PCML (1) LVDS (1) HyperTransport technology (1)
(1)
-6 Speed -7 Speed -8 Speed Grade Grade Grade
350 350 350 350 250 350 645 275 645 500 300 300 300 300 200 300 622 275 622 450 300 300 300 300 200 300 622 275 622 450
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Note to Tables 4-114 through 4-119:
These parameters are only available on row I/O pins.
Tables 4-120 through 4-123 show the maximum output clock rate for column and row pins in Stratix devices.
Table 4-120. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins in Flip-Chip Packages (Part 1 of 2) I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I (3) SSTL-2 Class I (4) SSTL-2 Class I (5)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
350 350 250 225 350 200 200 200 200 200 200 150 300 300 250 200 300 167 167 167 167 200 200 134 250 300 250 200 250 125 125 167 167 167 167 134 250 300 250 200 250 125 125 133 133 167 167 134
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Altera Corporation July 2005
4-81 Stratix Device Handbook, Volume 1
Timing Model
Table 4-120. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins in Flip-Chip Packages (Part 2 of 2) I/O Standard
SSTL-2 Class II (3) SSTL-2 Class II (4) SSTL-2 Class II (5) SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential 1.5-V HSTL C1 Differential 1.8-V HSTL Class I Differential 1.8-V HSTL Class II Differential SSTL-2 (6) LVPECL (2) PCML (2) LVDS (2) HyperTransport technology (2)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
200 200 150 150 150 250 225 250 225 350 350 350 350 350 200 225 250 225 200 500 350 500 350 200 200 134 133 133 225 200 225 200 300 300 300 300 300 200 200 225 200 200 500 350 500 350 167 167 134 133 133 200 200 200 200 250 250 250 250 250 200 200 200 200 167 500 350 500 350 167 167 134 133 133 200 200 200 200 250 250 250 250 250 200 200 200 200 167 500 350 500 350
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
4-82 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-121. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2, 3, 4] Pins in Flip-Chip Packages I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT LVPECL (2) PCML (2) LVDS (2) HyperTransport technology (2)
-5 Speed -6 Speed -7 Speed -8 Speed Grade Grade Grade Grade
400 400 400 350 400 200 200 167 167 150 150 150 150 250 225 250 225 250 225 400 400 400 300 717 420 717 420 350 350 350 300 350 167 167 150 150 133 133 133 133 225 225 225 225 225 225 350 350 350 250 717 420 717 420 300 300 300 300 300 125 125 133 133 133 133 133 133 200 200 200 200 200 200 300 300 300 200 500 420 500 420 300 300 300 300 300 125 125 133 133 133 133 133 133 200 200 200 200 200 200 300 300 300 200 500 420 500 420
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Altera Corporation July 2005
4-83 Stratix Device Handbook, Volume 1
Timing Model
Table 4-122. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins in Wire-Bond Packages (Part 1 of 2) I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT Differential 1.5-V HSTL C1 Differential 1.8-V HSTL Class I Differential 1.8-V HSTL Class II Differential SSTL-2 (1) LVPECL (2) PCML (2)
-6 Speed -7 Speed -8 Speed Grade Grade Grade
175 175 175 175 175 125 125 110 133 166 133 110 110 167 167 167 167 167 167 175 175 175 125 167 167 167 110 311 250 150 150 150 150 150 100 100 90 125 133 100 100 100 167 133 167 133 167 133 150 150 150 100 133 167 133 100 275 200 150 150 150 150 150 100 100 90 125 133 100 100 100 167 133 167 133 167 133 150 150 150 100 133 167 133 100 275 200
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
4-84 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-122. Stratix Maximum Output Clock Rate for PLL[5, 6, 11, 12] Pins in Wire-Bond Packages (Part 2 of 2) I/O Standard
LVDS (2) HyperTransport technology (2)
-6 Speed -7 Speed -8 Speed Grade Grade Grade
311 311 275 275 275 275
Unit
MHz MHz
Table 4-123. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2, 3, 4] Pins in Wire-Bond Packages (Part 1 of 2) I/O Standard
LVTTL 2.5 V 1.8 V 1.5 V LVCMOS GTL GTL+ SSTL-3 Class I SSTL-3 Class II SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I 1.8-V HSTL Class II 3.3-V PCI 3.3-V PCI-X 1.0 Compact PCI AGP 1x AGP 2x CTT LVPECL (2) PCML (2)
-6 Speed -7 Speed -8 Speed Grade Grade Grade
200 200 200 200 200 125 125 110 150 90 110 110 110 225 200 225 200 200 200 200 200 200 125 311 400 175 175 175 175 175 100 100 90 133 80 100 100 100 200 167 200 167 175 175 175 175 175 100 270 311 175 175 175 175 175 100 100 90 133 80 100 100 100 200 167 200 167 175 175 175 175 175 100 270 311
Unit
MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz
Altera Corporation July 2005
4-85 Stratix Device Handbook, Volume 1
Timing Model
Table 4-123. Stratix Maximum Output Clock Rate (Using I/O Pins) for PLL[1, 2, 3, 4] Pins in Wire-Bond Packages (Part 2 of 2) I/O Standard
LVDS (2) HyperTransport technology (2)
(1) (2) (3) (4) (5) (6)
-6 Speed -7 Speed -8 Speed Grade Grade Grade
400 420 311 400 311 400
Unit
MHz MHz
Notes to Tables 4-120 through 4-123:
Differential SSTL-2 outputs are only available on column clock pins. These parameters are only available on row I/O pins. SSTL-2 in maximum drive strength condition. See Table 4-101 on page 4-62 for more information on exact loading conditions for each I/O standard. SSTL-2 in minimum drive strength with 10pF output load condition. SSTL-2 in minimum drive strength with > 10pF output load condition. Differential SSTL-2 outputs are only supported on column clock pins.
4-86 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
High-Speed I/O Specification
Table 4-124 provides high-speed timing specifications definitions.
Table 4-124. High-Speed Timing Specifications & Terminology High-Speed Timing Specification
tC fHSCLK tRISE tFALL Timing unit interval (TUI)
Terminology
High-speed receiver/transmitter input and output clock period. High-speed receiver/transmitter input and output clock frequency. Low-to-high transmission time. High-to-low transmission time. The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency x Multiplication Factor) = tC/w). Maximum LVDS data transfer rate (fHSDR = 1/TUI). The timing difference between the fastest and slowest output edges, including tCO variation and clock skew. The clock is included in the TCCS measurement. The period of time during which the data must be valid to be captured correctly. The setup and hold times determine the ideal strobe position within the sampling window. SW = tSW (max) - tSW (min). Peak-to-peak input jitter on high-speed PLLs. Peak-to-peak output jitter on high-speed PLLs. Duty cycle on high-speed transmitter output clock. Lock time for high-speed transmitter and receiver PLLs. Deserialization factor (width of internal data bus). PLL multiplication factor.
fHSDR Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter (peak-to-peak) Output jitter (peak-to-peak) tDUTY tLOCK J W
Altera Corporation July 2005
4-87 Stratix Device Handbook, Volume 1
Tables 4-125 and 4-126 show the high-speed I/O timing for Stratix devices.
High-Speed I/O Specification
4-88 Stratix Device Handbook, Volume 1 Altera Corporation July 2005
Table 4-125. High-Speed I/O Specifications for Flip-Chip Packages (Part 1 of 4) Notes (1), (2) -5 Speed Grade Symbol
fHSCLK (Clock frequency) (LVDS, LVPECL, HyperTransport technology) fHSCLK = fHSDR / W
-6 Speed Grade Min
10 50 150 100 300 300 300 300 300 100 100
-7 Speed Grade Min
10 50 150 100 300 300 300 300 300 100 100
-8 Speed Grade Unit Min
10 50 150 100 300 300 300 300 300 100 100
Conditions Min
W = 4 to 30 (Serdes used) W = 2 (Serdes bypass) W = 2 (Serdes used) W = 1 (Serdes bypass) W = 1 (Serdes used) 10 50 150 100 300 300 300 300 300 100 100
Typ
Max
210 231 420 462 717 840 840 840 840 462 462
Typ
Max
210 231 420 462 717 840 840 840 840 462 462
Typ
Max
156 231 312 462 624 640 640 640 640 640 640
Typ
Max
115.5 231 231 462 462 462 462 462 462 462 462 MHz MHz MHz MHz MHz Mbps Mbps Mbps Mbps Mbps Mbps
fHSDR Device operation (LVDS, LVPECL, HyperTransport technology)
J = 10 J=8 J=7 J=4 J=2 J = 1 (LVDS and LVPECL only)
High-Speed I/O Specification
Altera Corporation July 2005 4-89 Stratix Device Handbook, Volume 1
Table 4-125. High-Speed I/O Specifications for Flip-Chip Packages (Part 2 of 4) Notes (1), (2) -5 Speed Grade Symbol
fHSCLK (Clock frequency) (PCML) fHSCLK = fHSDR / W
-6 Speed Grade Min
10 50 150 100 300 300 300 300 300 100 100
-7 Speed Grade Min
10 50 150 100 300 300 300 300 300 100 100
-8 Speed Grade Unit Min
10 50 150 100 300 300 300 300 300 100 100
Conditions Min
W = 4 to 30 (Serdes used) W = 2 (Serdes bypass) W = 2 (Serdes used) W = 1 (Serdes bypass) W = 1 (Serdes used) 10 50 150 100 300 300 300 300 300 100 100
Typ
Max
100 200 200 250 400 400 400 400 400 400 250 200
Typ
Max
100 200 200 250 400 400 400 400 400 400 250 200
Typ
Max
77.75 150 155.5 200 311 311 311 311 311 300 200 300
Typ
Max
77.75 150 155.5 200 311 311 311 311 311 300 200 300 MHz MHz MHz MHz MHz Mbps Mbps Mbps Mbps Mbps Mbps ps
fHSDR Device operation (PCML)
J = 10 J=8 J=7 J=4 J=2 J=1
TCCS
All
High-Speed I/O Specification
4-90 Stratix Device Handbook, Volume 1 Altera Corporation July 2005
Table 4-125. High-Speed I/O Specifications for Flip-Chip Packages (Part 3 of 4) Notes (1), (2) -5 Speed Grade Symbol
SW
-6 Speed Grade Min
750 900 1,500 500 440
-7 Speed Grade Min
800 1,200 1,700 550 500
-8 Speed Grade Unit Min
800 1,200 1,700 550 500
Conditions Min
PCML (J = 4, 7, 8, 10) PCML (J = 2) PCML (J = 1) LVDS and LVPECL (J = 1) LVDS, LVPECL, HyperTransport technology (J = 2 through 10) 750 900 1,500 500 440
Typ
Max
Typ
Max
Typ
Max
Typ
Max
ps ps ps ps ps
Input jitter tolerance (peak-to-peak) Output jitter (peak-to-peak) Output tRISE
All
250
250
250
250
ps
All LVDS HyperTransport technology LVPECL PCML 80 110 90 80 80 110 90 105 110 170 130 110 110 170 130 140
160 120 200 150 135 120 200 160 175 80 110 90 80 80 110 90 105 110 170 130 110 110 170 130 140
160 120 200 150 135 120 200 160 175 80 120 100 80 80 110 100 110 110 170 135 110 110 170 135 145
200 120 200 150 135 120 200 160 175 80 120 100 80 80 110 100 110 110 170 135 110 110 170 135 145
200 120 200 150 135 120 200 160 175
ps ps ps ps ps ps ps ps ps
Output tFALL
LVDS HyperTransport technology LVPECL PCML
High-Speed I/O Specification
Altera Corporation July 2005 4-91 Stratix Device Handbook, Volume 1
Table 4-125. High-Speed I/O Specifications for Flip-Chip Packages (Part 4 of 4) Notes (1), (2) -5 Speed Grade Symbol
tDUTY
-6 Speed Grade Min
47.5 45
-7 Speed Grade Min
47.5 45
-8 Speed Grade Unit Min
47.5 45
Conditions Min
LVDS (J = 2 through 10) LVDS (J =1) and LVPECL, PCML, HyperTransport technology 47.5 45
Typ
50 50
Max
52.5 55
Typ
50 50
Max
52.5 55
Typ
50 50
Max
52.5 55
Typ
50 50
Max
52.5 55 % %
tLOCK
(1) (2)
All
100
100
100
100
s
Notes to Table 4-125:
When J = 4, 7, 8, and 10, the SERDES block is used. When J = 2 or J = 1, the SERDES is bypassed.
High-Speed I/O Specification
4-92 Stratix Device Handbook, Volume 1 Altera Corporation July 2005
Table 4-126. High-Speed I/O Specifications for Wire-Bond Packages (Part 1 of 2) -6 Speed Grade Symbol
fHSCLK (Clock frequency) (LVDS,LVPECL, HyperTransport technology) fHSCLK = fHSDR / W fHSDR Device operation, (LVDS,LVPECL, HyperTransport technology)
-7 Speed Grade Min
10 50 150 100 300 300 300 300 300 100 100
-8 Speed Grade Unit Min
10 50 150 100 300 300 300 300 300 100 100
Conditions Min
W = 4 to 30 (Serdes used) W = 2 (Serdes bypass) W = 2 (Serdes used) W = 1 (Serdes bypass) W = 1 (Serdes used) J = 10 J=8 J=7 J=4 J=2 J = 1 (LVDS and LVPECL only) 10 50 150 100 300 300 300 300 300 100 100 10 50 150 100 300 300 300 300 300 100 100
Typ
Max
156 231 312 311 624 624 624 624 624 462 311 77.75 150 155.5 200 311 311 311 311 311 300 200 400
Typ
Max
115.5 231 231 270 462 462 462 462 462 462 270
Typ
Max
115.5 231 231 270 462 462 462 462 462 462 270 MHz MHz MHz MHz MHz Mbps Mbps Mbps Mbps Mbps Mbps MHz
fH S C L K (Clock frequency) (PCML) fHSCLK = fHSDR / W
W = 4 to 30 (Serdes used) W = 2 (Serdes bypass) W = 2 (Serdes used) W = 1 (Serdes bypass) W = 1 (Serdes used)
50
77.5
50
77.5
MHz MHz
100
155
100
155
MHz MHz Mbps Mbps Mbps Mbps
Device operation, fH S D R (PCML)
J = 10 J=8 J=7 J=4 J=2 J=1
100 100
155 155 400
100 100
155 155 400
Mbps Mbps ps
TCCS
All
High-Speed I/O Specification
Altera Corporation July 2005 4-93 Stratix Device Handbook, Volume 1
Table 4-126. High-Speed I/O Specifications for Wire-Bond Packages (Part 2 of 2) -6 Speed Grade Symbol
SW
-7 Speed Grade Min
800 1,200 1,700 550 500
-8 Speed Grade Unit Min
800 1,200 1,700 550 500
Conditions Min
PCML (J = 4, 7, 8, 10) only PCML (J = 2) only PCML (J = 1) only LVDS and LVPECL (J = 1) only LVDS, LVPECL, HyperTransport technology (J = 2 through 10) only 800 1,200 1,700 550 500
Typ
Max
Typ
Max
Typ
Max
ps ps ps ps ps
Input jitter tolerance (peak-to-peak) Output jitter (peak-topeak) Output tR I S E
All All LVDS HyperTransport technology LVPECL PCML 80 120 100 80 80 110 100 110 47.5 45 110 170 135 110 110 170 135 145 50 50
250 200 120 200 150 135 120 200 160 175 52.5 55 80 120 100 80 80 110 100 110 47.5 45 110 170 135 110 110 170 135 145 50 50
250 200 120 200 150 135 120 200 160 175 52.5 55 80 120 100 80 80 110 100 110 47.5 45 110 170 135 110 110 170 135 145 50 50
250 200 120 200 150 135 120 200 160 175 52.5 55
ps ps ps ps ps ps ps ps ps ps % %
Output tFA L L
LVDS HyperTransport LVPECL PCML
tD U T Y
LVDS (J = 2 through10) only LVDS (J =1) and LVPECL, PCML, HyperTransport technology
tL O C K
All
100
100
100
s
PLL Specifications
PLL Specifications
Tables 4-127 through 4-129 describe the Stratix device enhanced PLL specifications.
Table 4-127. Enhanced PLL Specifications for -5 Speed Grades (Part 1 of 2) Symbol
fIN fINPFD fINDUTY fEINDUTY tINJITTER tEINJITTER tFCOMP fOUT fOUT_EXT tOUTDUTY tJITTER tCONFIG5,6 tCONFIG11,12 tSCANCLK tDLOCK
Parameter
Input clock frequency Input frequency to PFD Input clock duty cycle External feedback clock input duty cycle Input clock period jitter External feedback clock period jitter External feedback clock compensation time (4) Output frequency for internal global or regional clock Output frequency for external clock (3) Duty cycle for external clock output (when set to 50%) Period jitter for external clock output (6) Time required to reconfigure the scan chains for PLLs 5 and 6 Time required to reconfigure the scan chains for PLLs 11 and 12 scanclk frequency (5) Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) (7) Time required to lock from end of device configuration PLL internal VCO operating range Clock skew between two external clock outputs driven by the same counter
Min
3 (1), (2) 3 40 40
Typ
Max
684 420 60 60 200 (3) 200 (3) 6
Unit
MHz MHz % % ps ps ns MHz MHz % ps or mUI
0.3 0.3 45
500 526 55 100 ps for >200-MHz outclk 20 mUI for <200-MHz outclk 289/fSCANCLK 193/fSCANCLK 22 100
MHz s
tLOCK fVCO tLSKEW
10 300 50
400 800 (8)
s MHz ps
4-94 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-127. Enhanced PLL Specifications for -5 Speed Grades (Part 2 of 2) Symbol
tSKEW
Parameter
Clock skew between two external clock outputs driven by the different counters with the same settings Spread spectrum modulation frequency Percentage spread for spread spectrum frequency (10) Minimum pulse width on areset signal Minimum pulse width on the areset signal when using PLL reconfiguration. Reset the PLL after scandataout goes high.
Min
Typ
75
Max
Unit
ps
fSS % spread tARESET tA R E S E T _ R E C O N FIG
30 0.4 10 500 0.5
150 0.6
kHz % ns ns
Table 4-128. Enhanced PLL Specifications for -6 Speed Grades Symbol
fIN fINPFD fINDUTY fEINDUTY tINJITTER tEINJITTER tFCOMP fOUT fOUT_EXT tOUTDUTY tJITTER tCONFIG5,6
(Part 1 of 2) Max
650 420 60 60 200 (3) 200 (3) 6
Parameter
Input clock frequency Input frequency to PFD Input clock duty cycle External feedback clock input duty cycle Input clock period jitter External feedback clock period jitter External feedback clock compensation time (4) Output frequency for internal global or regional clock Output frequency for external clock (3) Duty cycle for external clock output (when set to 50%) Period jitter for external clock output (6) Time required to reconfigure the scan chains for PLLs 5 and 6
Min
3 (1), (2) 3 40 40
Typ
Unit
MHz MHz % % ps ps ns MHz MHz % ps or mUI
0.3 0.3 45
450 500 55 100 ps for >200-MHz outclk 20 mUI for <200-MHz outclk 289/fSCANCLK 193/fSCANCLK
tCONFIG11,12 Time required to reconfigure the scan chains for PLLs 11 and 12
Altera Corporation July 2005
4-95 Stratix Device Handbook, Volume 1
PLL Specifications
Table 4-128. Enhanced PLL Specifications for -6 Speed Grades Symbol
tSCANCLK tDLOCK
(Part 2 of 2) Max
22
Parameter
scanclk frequency (5) Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) (7) (11) Time required to lock from end of device configuration (11) PLL internal VCO operating range Clock skew between two external clock outputs driven by the same counter Clock skew between two external clock outputs driven by the different counters with the same settings Spread spectrum modulation frequency Percentage spread for spread spectrum frequency (10) Minimum pulse width on areset signal
Min
(9)
Typ
Unit
MHz s
100
tLOCK fVCO tLSKEW
10 300 50
400 800 (8)
s MHz ps
tSKEW
75
ps
fSS % spread tARESET
30 0.4 10 0.5
150 0.6
kHz % ns
Table 4-129. Enhanced PLL Specifications for -7 Speed Grade (Part 1 of 2) Symbol
fIN fINPFD fINDUTY fEINDUTY tINJITTER tEINJITTER tFCOMP fOUT fOUT_EXT
Parameter
Input clock frequency Input frequency to PFD Input clock duty cycle External feedback clock input duty cycle Input clock period jitter External feedback clock period jitter External feedback clock compensation time (4) Output frequency for internal global or regional clock Output frequency for external clock (3)
Min
3 (1), (2) 3 40 40
Typ
Max
565 420 60 60 200 (3) 200 (3) 6
Unit
MHz MHz % % ps ps ns MHz MHz
0.3 0.3
420 434
4-96 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-129. Enhanced PLL Specifications for -7 Speed Grade (Part 2 of 2) Symbol
tOUTDUTY tJITTER tCONFIG5,6 tCONFIG11,12 tSCANCLK tDLOCK
Parameter
Duty cycle for external clock output (when set to 50%) Period jitter for external clock output (6) Time required to reconfigure the scan chains for PLLs 5 and 6 Time required to reconfigure the scan chains for PLLs 11 and 12 scanclk frequency (5) Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) (7) (11) Time required to lock from end of device configuration (11) PLL internal VCO operating range Clock skew between two external clock outputs driven by the same counter Clock skew between two external clock outputs driven by the different counters with the same settings Spread spectrum modulation frequency Percentage spread for spread spectrum frequency (10) Minimum pulse width on areset signal
Min
45
Typ
Max
55 100 ps for >200-MHz outclk 20 mUI for <200-MHz outclk 289/fSCANCLK 193/fSCANCLK 22
Unit
% ps or mUI
MHz s
(9)
100
tLOCK fVCO tLSKEW
10 300 50
400 600 (8)
s MHz ps
tSKEW
75
ps
fSS % spread tARESET
30 0.5 10
150 0.6
kHz % ns
Table 4-130. Enhanced PLL Specifications for -8 Speed Grade (Part 1 of 3) Symbol
fIN fINPFD fINDUTY fEINDUTY tINJITTER
Parameter
Input clock frequency Input frequency to PFD Input clock duty cycle External feedback clock input duty cycle Input clock period jitter
Min
3 (1), (2) 3 40 40
Typ
Max
480 420 60 60 200 (3)
Unit
MHz MHz % % ps
Altera Corporation July 2005
4-97 Stratix Device Handbook, Volume 1
PLL Specifications
Table 4-130. Enhanced PLL Specifications for -8 Speed Grade (Part 2 of 3) Symbol
tEINJITTER tFCOMP fOUT fOUT_EXT tOUTDUTY tJITTER tCONFIG5,6 tCONFIG11,12 tSCANCLK tDLOCK
Parameter
External feedback clock period jitter External feedback clock compensation time (4) Output frequency for internal global or regional clock Output frequency for external clock (3) Duty cycle for external clock output (when set to 50%) Period jitter for external clock output (6) Time required to reconfigure the scan chains for PLLs 5 and 6 Time required to reconfigure the scan chains for PLLs 11 and 12 scanclk frequency (5) Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) (7) (11) Time required to lock from end of device configuration (11) PLL internal VCO operating range
Min
Typ
Max
200 (3) 6
Unit
ps ns MHz MHz % ps or mUI
0.3 0.3 45
357 369 55 100 ps for >200-MHz outclk 20 mUI for <200-MHz outclk 289/fSCANCLK 193/fSCANCLK 22
MHz s
(9)
100
tLOCK fVCO
10 300
400 600 (8)
s MHz
4-98 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-130. Enhanced PLL Specifications for -8 Speed Grade (Part 3 of 3) Symbol
tLSKEW
Parameter
Clock skew between two external clock outputs driven by the same counter Clock skew between two external clock outputs driven by the different counters with the same settings Spread spectrum modulation frequency Percentage spread for spread spectrum frequency (10) Minimum pulse width on areset signal
Min
Typ
50
Max
Unit
ps
tSKEW
75
ps
fSS % spread tARESET
30 0.5 10
150 0.6
kHz % ns
Notes to Tables 4-127 through 4-130:
The minimum input clock frequency to the PFD (fIN/N) must be at least 3 MHz for Stratix device enhanced PLLs. Use this equation (fOUT = fI N * ml(n x post-scale counter)) in conjunction with the specified fI N P F D and fV C O ranges to determine the allowed PLL settings. (3) See "Maximum Input & Output Clock Rates" on page 4-76. (4) tFCOMP can also equal 50% of the input clock period multiplied by the pre-scale divider n (whichever is less). (5) This parameter is timing analyzed by the Quartus II software because the scanclk and scandata ports can be driven by the logic array. (6) Actual jitter performance may vary based on the system configuration. (7) Total required time to reconfigure and lock is equal to tDLOCK + tCONFIG. If only post-scale counters and delays are changed, then tDLOCK is equal to 0. (8) When using the spread-spectrum feature, the minimum VCO frequency is 500 MHz. The maximum VCO frequency is determined by the speed grade selected. (9) Lock time is a function of PLL configuration and may be significantly faster depending on bandwidth settings or feedback counter change increment. (10) Exact, user-controllable value depends on the PLL settings. (11) The LOCK circuit on Stratix PLLs does not work for industrial devices below -20C unless the PFD frequency > 200 MHz. See the Stratix FPGA Errata Sheet for more information on the PLL. (1) (2)
Altera Corporation July 2005
4-99 Stratix Device Handbook, Volume 1
PLL Specifications
Tables 4-131 through 4-133 describe the Stratix device fast PLL specifications.
Table 4-131. Fast PLL Specifications for -5 & -6 Speed Grade Devices Symbol
fIN fINPFD fOUT fOUT_DIFFIO
Parameter
CLKIN frequency (1), (2), (3) Input frequency to PFD Output frequency for internal global or regional clock (3) Output frequency for external clock driven out on a differential I/O data channel (2) VCO operating frequency CLKIN duty cycle Period jitter for CLKIN pin Duty cycle for DFFIO 1x CLKOUT pin (6) Period jitter for DIFFIO clock out (6) Time required for PLL to acquire lock Multiplication factors for m counter (6) Multiplication factors for l0, l1, and g0 counter (7), (8) Minimum pulse width on areset signal
Min
10 10 9.375 (5)
Max
717 500 420 (5)
Unit
MHz MHz MHz
fVCO tINDUTY tINJITTER tDUTY tJITTER tLOCK m l0, l1, g0 tARESET
300 40
1,000 60 200
MHz % ps % ps s Integer Integer ns
45
55 (5)
10 1 1 10
100 32 32
Table 4-132. Fast PLL Specifications for -7 Speed Grades (Part 1 of 2) Symbol
fIN fINPFD fOUT fOUT_DIFFIO
Parameter
CLKIN frequency (1), (3) Input frequency to PFD Output frequency for internal global or regional clock (4) Output frequency for external clock driven out on a differential I/O data channel VCO operating frequency CLKIN duty cycle Period jitter for CLKIN pin Duty cycle for DFFIO 1x CLKOUT pin (6)
Min
10 10 9.375 (5)
Max
640 500 420 (5)
Unit
MHz MHz MHz MHz
fVCO tINDUTY tINJITTER tDUTY
300 40
700 60 200
MHz % ps %
45
55
4-100 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
DC & Switching Characteristics
Table 4-132. Fast PLL Specifications for -7 Speed Grades (Part 2 of 2) Symbol
tJITTER tLOCK m l0, l1, g0 tARESET
Parameter
Period jitter for DIFFIO clock out (6) Time required for PLL to acquire lock Multiplication factors for m counter (7) Multiplication factors for l0, l1, and g0 counter (7), (8) Minimum pulse width on areset signal
Min
Max
(5)
Unit
ps s Integer Integer ns
10 1 1 10
100 32 32
Table 4-133. Fast PLL Specifications for -8 Speed Grades (Part 1 of 2) Symbol
fIN fINPFD fOUT fOUT_DIFFIO
Parameter
CLKIN frequency (1), (3) Input frequency to PFD Output frequency for internal global or regional clock (4) Output frequency for external clock driven out on a differential I/O data channel VCO operating frequency CLKIN duty cycle Period jitter for CLKIN pin Duty cycle for DFFIO 1x CLKOUT pin (6) Period jitter for DIFFIO clock out (6) Time required for PLL to acquire lock Multiplication factors for m counter (7) Multiplication factors for l0, l1, and g0 counter (7), (8)
Min
10 10 9.375 (5)
Max
460 500 420 (5)
Unit
MHz MHz MHz MHz
fVCO tINDUTY tINJITTER tDUTY tJITTER tLOCK m l0, l1, g0
300 40
700 60 200
MHz % ps % ps s Integer Integer
45
55 (5)
10 1 1
100 32 32
Altera Corporation July 2005
4-101 Stratix Device Handbook, Volume 1
DLL Jitter
Table 4-133. Fast PLL Specifications for -8 Speed Grades (Part 2 of 2) Symbol
tARESET
Parameter
Minimum pulse width on areset signal
Min
10
Max
Unit
ns
Notes to Tables 4-131 through 4-133:
(1) (2) (3) (4) See "Maximum Input & Output Clock Rates" on page 4-76. PLLs 7, 8, 9, and 10 in the EP1S80 device support up to 717-MHz input and output. Use this equation (fO U T = fI N * ml(n x post-scale counter)) in conjunction with the specified fI N P F D and fV C O ranges to determine the allowed PLL settings. When using the SERDES, high-speed differential I/O mode supports a maximum output frequency of 210 MHz to the global or regional clocks (that is, the maximum data rate 840 Mbps divided by the smallest SERDES J factor of 4). Refer to the section "High-Speed I/O Specification" on page 4-87 for more information. This parameter is for high-speed differential I/O mode only. These counters have a maximum of 32 if programmed for 50/50 duty cycle. Otherwise, they have a maximum of 16. High-speed differential I/O mode supports W = 1 to 16 and J = 4, 7, 8, or 10.
(5) (6) (7) (8)
DLL Jitter
Table 4-134 reports the jitter for the DLL in the DQS phase shift reference circuit.
Table 4-134. DLL Jitter for DQS Phase Shift Reference Circuit Frequency (MHz)
197 to 200 160 to 196 100 to 159 100 300 500
DLL Jitter (ps)
f
For more information on DLL jitter, see the DDR SRAM section in the Stratix Architecture chapter of the Stratix Device Handbook, Volume 1.
4-102 Stratix Device Handbook, Volume 1
Altera Corporation July 2005
5. Reference & Ordering Information
S51005-2.1
Software
Stratix(R) devices are supported by the Altera(R) Quartus(R) II design software, which provides a comprehensive environment for system-on-aprogrammable-chip (SOPC) design. The Quartus II software includes HDL and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, SignalTap(R) II logic analyzer, and device configuration. See the Design Software Selector Guide for more details on the Quartus II software features. The Quartus II software supports the Windows XP/2000/NT/98, Sun Solaris, Linux Red Hat v7.1 and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the NativeLink(R) interface.
Device Pin-Outs Ordering Information
Stratix device pin-outs can be found on the Altera web site (www.altera.com). Figure 5-1 describes the ordering codes for Stratix devices. For more information on a specific package, see the Package Information for Stratix Devices chapter.
Altera Corporation September 2004
5-1
Ordering Information
Figure 5-1. Stratix Device Packaging Ordering Information
EP1S Family Signature EP1S: Stratix 80 F 1508 C 7 ES Optional Suffix Indicates specific device options or shipment method. ES: Engineering sample
Device Type 10 20 25 30 40 60 80 Speed Grade 5, 6, or 7, with 5 being the fastest
Operating Temperature C: Commercial temperature (tJ = 0 C to 85 C) I: Industrial temperature (tJ = -40 C to 100 C) Package Type Pin Count Number of pins for a particular BGA or FineLine BGA package
B: Ball-grid array (BGA) F: FineLine BGA
5-2 Stratix Device Handbook, Volume 1
Altera Corporation September 2004
Index
A
Accumulator 2-63 Adder/Output Blocks 2-61 Adder/Subtractor 2-63 Accumulator 2-63 AGP 1x Specifications 4-13 AGP 2x Specifications 4-13 Architecture 2-1 36 x 36 Multiply Mode 2-66 addnsub Signal 2-8 Block Diagram 2-2 Bus Hold 2-121 Byte Alignment 2-140 Carry-Select Chain 2-11 Clear & Preset Logic Control 2-13 Combined Resources 2-78 Dedicated Circuitry 2-137 Device Resources 2-3 Device Routing Scheme 2-20 Digital Signal Processing Block 2-52 Direct Link Connection 2-5 Dynamic Arithmetic Mode 2-10 in LE 2-11 Four-Multipliers Adder Mode 2-68 Functional Description 2-1 LAB Interconnects 2-4 Logic Array Blocks 2-3 Structure 2-4 LE Operating Modes 2-8 Logic Elements 2-6 Modes of Operation 2-64 Multiplier Size & Configurations per DSP block 2-70 Multiply-Accumulator Mode 2-67 MultiTrack Interconnect 2-14 Normal Mode 2-9 in LE 2-9
Altera Corporation
Open-Drain Output 2-120 Power Sequencing & Hot Socketing 2-140 Programmable Drive Strength 2-119 Programmable Pull-Up Resistor 2-122 Simple Multiplier Mode 2-64 Single-Port Mode 2-51 Slew-Rate Control 2-120 Two-Multipliers Adder Mode 2-67 Adder Mode Implementing Complex Multiply 2-68
C
Class I Specifications 4-11, 4-12 Class II Specifications 4-11, 4-12, 4-13 Clocks Clock Feedback 2-96 Clock Multiplication & Division 2-88, 2-101 Clock Switchover 2-88 Delay 2-97 EP1S10, EP1S20 & EP1S25 Device I/O Clock Groups 2-80 EP1S25, EP1S20 & EP1S10 Device Fast Clock Pin Connections to Fast Regional Clocks 2-77 EP1S30 Device Fast Regional Clock Pin Connections to Fast Regional Clocks 2-78 EP1S30, EP1S40, EP1S60, EP1S80 Device I/O Clock Groups 2-81 External Clock Inputs 2-102 Outputs 2-92, 2-103 Outputs for Enhanced PLLs 11 & 12 2-95 Outputs for PLLs 5 & 6 2-93 Fast Regional Clock External I/O Timing Parameters 4-34 Fast Regional Clock Network 2-76
Index-1
Stratix Device Handbook, Volume 1
Global & Hierarchical Clocking 2-73 Global & Regional Clock Connections from Side Pins & Fast PLL Outputs 2-85 from Top Clock Pins & Enhanced PLL Outputs 2-86 Global Clock External I/O Timing Parameters 4-35 Global Clock Network 2-74 Global Clocking 2-75 Independent Clock Mode 2-44 Input/Output Clock Mode 2-46 Simple Dual-Port Mode 2-48 True Dual-Port Mode 2-47 Maximum Input & Output Clock Rates 4-76 Maximum Input Clock Rate for CLK (0, 2, 9, 11) Pins in
Flip-Chip Packages Wire-Bond Packages
(1, 3, 8, 10) Pins in
4-77 4-79
Flip-Chip Packages Wire-Bond Packages
(7..4) & CLK(15..12) Pins in
4-78 4-80
4-84 Phase & Delay Shifting 2-96 Phase Delay 2-96 PLL Clock Networks 2-73 Read/Write Clock Mode 2-49 in Simple Dual-Port Mode 2-50 Regional Clock 2-75 External I/O Timing Parameters 4-34 Regional Clock Bus 2-79 Regional Clock Network 2-75 Spread-Spectrum Clocking 2-98 Configuration 3-5 32-Bit IDCODE 3-3 and Testing 3-1 Data Sources for Configuration 3-7 Local Update Mode 3-12 Local Update Transition Diagram 3-12 Operating Modes 3-5 Partial Reconfiguration 3-7 Remote Update 3-8 Remote Update Transition Diagram 3-11 Schemes 3-7 SignalTap II Embedded Logic Analyzer 3-5 Stratix FPGAs with JRunner 3-7 Control Signals 2-104
Packages Wire-Bond Packages
4-81
Flip-Chip Packages Wire-Bond Packages
Maximum Output Clock Rate for PLL (1, 2, 3, 4) Pins in
D
4-76 4-78 DC Switching Absolute Maximum Ratings 4-1 Bus Hold Parameters 4-16 Capacitance 4-17 DC & Switching Characteristics 4-1 External Timing Parameters 4-33 Operating Conditions 4-1 Performance 4-20 Power Consumption 4-17 Recommended Operating Conditions 4-1 DDR Double-Data Rate I/O Pins 2-111 Device Features EP1S10, EP1S20, EP1S25, EP1S30, 1-3 EP1S40, EP1S60, EP1S80, 1-3
Flip-Chip Packages Wire-Bond Packages
(5, 6, 11, 12) Pins in
4-83 4-85
Flip-Chip
Index-2
Altera Corporation
Stratix Device Handbook, Volume 1
Differential HSTL Specifications 4-15 DSP Block Diagram Configuration for 18 x 18-Bit 2-55 for 9 x 9-Bit 2-56 Block Interconnect Interface 2-71 Block Interface 2-70 Block Signal Sources & Destinations 2-73 Blocks Arranged in Columns 2-53 in Stratix Devices 2-54 Input Register Modes 2-60 Input Registers 2-58 Multiplier 2-60 Block 2-57 Signed Representation 2-60 Sub-Block 2-57 Sub-Blocks Using Input Shift Register Connections 2-59 Pipeline/Post Multiply Register 2-61
E
EP1S10 Devices Column Pin Fast Regional Clock External I/O Parameters 4-36 Global Clock External I/O Parameters 4-37 Regional Clock External I/O Parameters 4-36 Row Pin Fast Regional Clock External I/O Parameters 4-37 Global Clock External I/O Parameters 4-38 Regional Clock External I/O Parameters 4-38 EP1S20 Devices Column Pin Fast Regional Clock External I/O Parameters 4-39 Global Clock External I/O Parameters 4-40 Regional Clock External I/O
Timing Timing Timing
Timing Timing Timing
Timing Timing Timing
Parameters 4-39 Row Pin Fast Regional Clock External I/O Parameters 4-40 Global Clock External I/O Parameters 4-41 Regional Clock External I/O Parameters 4-41 EP1S25 Devices Column Pin Fast Regional Clock External I/O Parameters 4-42 Global Clock External I/O Parameters 4-43 Regional Clock External I/O Parameters 4-42 Row Pin Fast Regional Clock External I/O Parameters 4-43 Global Clock External I/O Parameters 4-44 Regional Clock External I/O Parameters 4-44 EP1S30 Devices Column Pin Fast Regional Clock External I/O Parameters 4-45 Global Clock External I/O Parameters 4-45 Regional Clock External I/O Parameters 4-45 Row Pin Fast Regional Clock External I/O Parameters 4-46 Global Clock External I/O Parameters 4-47 Regional Clock External I/O Parameters 4-47 EP1S40 Devices Column Pin Fast Regional Clock External I/O Parameters 4-48 Global Clock External I/O Parameters 4-49 Regional Clock External I/O Parameters 4-48 Row Pin
Timing Timing Timing
Timing Timing Timing
Timing Timing Timing
Timing Timing Timing
Timing Timing Timing
Timing Timing Timing
Altera Corporation
Index-3
Stratix Device Handbook, Volume 1
Fast Regional Clock External I/O Parameters 4-49 Global Clock External I/O Parameters 4-50 Regional Clock External I/O Parameters 4-50 EP1S60 Devices Column Pin Fast Regional Clock External I/O Parameters 4-51 Global Clock External I/O Parameters 4-52 Regional Clock External I/O Parameters 4-51 M-RAM Interface Locations 2-38 Row Pin Fast Regional Clock External I/O Parameters 4-52 Global Clock External I/O Parameters 4-53 Regional Clock External I/O Parameters 4-53 EP1S80 Devices Column Pin Fast Regional Clock External I/O Parameters 4-54 Global Clock External I/O Parameters 4-55 Regional Clock External I/O Parameters 4-54 Global Clock External I/O Parameters 4-56 Row Pin Fast Regional Clock External I/O Parameters 4-55 Regional Clock External I/O Parameters 4-56
Timing Timing Timing
I
I/O Standards 1.5-V 4-14, 4-15 I/O Specifications 4-4 1.8-V I/O Specifications 4-4 2.5-V I/O Specifications 4-3 3.3-V 4-13 LVDS I/O Specifications 4-6 PCI Specifications 4-9 PCML Specifications 4-8 Advanced I/O Standard Support 2-122 Column I/O Block Connection to the Interconnect 2-107 Column Pin Input Delay Adders 4-66 Control Signal Selection per IOE 2-109 CTT I/O Specifications 4-16 Differential LVDS Input On-Chip Termination 2-128 External I/O Delay Parameters 4-66 GTL+ I/O Specifications 4-10 High-Speed Differential I/O Support 2-130 HyperTransport Technology Specifications 4-9 I/O Banks 2-125 I/O Structure 2-104 I/O Support by Bank 2-126 IOE Structure 2-105 LVCMOS Specifications 4-3 LVDS Performance on Fast PLL Input 2-103 LVPECL Specifications 4-8 LVTTL Specifications 4-3 MultiVolt I/O Interface 2-129 MultiVolt I/O Support 2-130 Output Delay Adders for Fast Slew Rate on Column Pins 4-68 Output Delay Adders for Fast Slew Rate on Row Pins 4-69 Output Delay Adders for Slow Slew Rate on Column Pins 4-70 Package Options & I/O Pin Counts 1-4 Receiver Input Waveforms for Differential
Timing Timing Timing
Timing Timing Timing
Timing Timing Timing Timing
Timing Timing
H
HSTL Class I Specifications 4-14, 4-15 Class II Specifications 4-14, 4-15
Index-4
Altera Corporation
Stratix Device Handbook, Volume 1
I/O Standards 4-5 I/O Block Connection to the Interconnect 2-106 Row Pin Input Delay Adders 4-67 Signal Path through the I/O Block 2-108 SSTL-18 4-11 SSTL-2 4-12 SSTL-3 4-12, 4-13 Stratix IOE in Bidirectional I/O Configuration 2-110 Supported I/O Standards 2-123 Transmitter Output Waveforms for Differential I/O Standards 4-6 Interconnect C4 Connections 2-18 DSP Block Interface to Interconnect 2-72 Left-Facing M-RAM to Interconnect Interface 2-40 LUT Chain Register Chain Interconnects 2-17 M-RAM Column Unit Interface to Interconnect 2-42 Row Unit Interface to Interconnect 2-41 R4 Connections 2-15 IOE Internal Timing Microparameters 4-29 Row
M
Memory Architecture Byte Enable for M4K RAM Block 2-32 Byte Enable for M-RAM Block 2-35 External RAM Interfacing 2-115 M4K Block Internal Timing Microparameter Descriptions 4-24 Microparameters 4-31 RAM Block 2-30 Configurations (Simple DualPort) 2-31 Configurations (True DualPort) 2-31 Control Signals 2-33 LAB Row Interface 2-33 M512 Block Internal Timing Microparameter Descriptions 4-24 Microparameters 4-30 RAM Block Architecture 2-27 Configurations (Simple Dual-Port RAM) 2-27 Control Signals 2-29 LAB Row Interface 2-30 Memory Block Size 2-26 Memory Modes 2-21 M-RAM Block 2-34 Configurations (Simple DualPort) 2-34 Configurations (True DualPort) 2-35 Block Control Signals 2-37 Block Internal Timing Microparameter Descriptions 4-25 Combined Byte Selection for x144
J
JTAG Boundary-Scan Register Length 3-3 Support 3-1 Stratix JTAG Instructions 3-2 Waveforms 3-4
L
LAB Control Signals 2-5 Wide Control Signals 2-6 LUT Chain & Register Chain 2-8
Altera Corporation
Index-5
Stratix Device Handbook, Volume 1
Mode 2-36 & Column Interface Unit Signals 2-43 Parity Bit Support 2-24 Shift Register Memory Configuration 2-26 Support 2-25 Simple Dual-Port & Single-Port Memory Configurations 2-23 Stratix IOE in DDR Input I/O Configuration 2-112 Stratix IOE in DDR Output I/O Configuration 2-114 TriMatrix Memory 2-21 True Dual-Port Memory Configuration 2-22 Row
Port I/O Standards 2-102 I/O Standards Supported for Enhanced PLL Pins 2-94 Lock Detect & Programmable Gated Locked 2-98 PLL Locations 2-84 Programmable Bandwidth 2-91 Programmable Delay Chain 2-111 Programmable Duty Cycle 2-98 Reconfiguration 2-90
T
Testing Temperature Sensing Diode 3-13 Electrical Characteristics 3-14 External 3-14 Temperature vs. Temperature-Sensing Diode Voltage 3-15 Timing DSP Block Internal Timing Microparameter Descriptions 4-23 Microparameters 4-29 Dual-Port RAM Timing Microparameter Waveform 4-27 External Timing in Stratix Devices 4-33 High-Speed I/O Timing 4-87 High-Speed Timing Specifications & Terminology 4-87 Internal Parameters 4-22 IOE Internal Timing Microparameter Descriptions 4-22 LE Internal Timing Microparameters 4-28 Logic Elements Internal Timing Microparameter Descriptions 4-22 Model 4-19 PLL Timing 4-94 Preliminary & Final 4-19 Stratix Device Timing Model Status 4-19 Stratix JTAG Timing Parameters & Values 3-4 TriMatrix Memory TriMatrix Memory Features 2-21
O
Ordering Information 5-1 Device Pin-Outs 5-1 Packaging Ordering Information 5-2 Reference & Ordering Information 5-1 Output Registers 2-64 Output Selection Multiplexer 2-64
P
Packaging BGA Package Sizes 1-4 Device Speed Grades 1-5 FineLine BGA Package Sizes 1-5 PCI-X 1.0 Specifications 4-10 Phase Shifting 2-103 PLL Advanced Clear & Enable Control 2-98 Dynamically Programmable Counters & Delays in Stratix Device Enhanced PLLs 2-91 Enhanced Fast PLLs 2-81 Fast PLL 2-100 Channel Layout EP1S10, EP1S20 or EP1S25 Devices 2-138 Channel Layout EP1S30 to EP1S80 Devices 2-139
Index-6
Altera Corporation

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